MT92220BG Zarlink Semiconductor, MT92220BG Datasheet - Page 135

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MT92220BG

Manufacturer Part Number
MT92220BG
Description
Description = 1023 Channel Voice Over IP/AAL2 Processor ;; Package Type = Epbga ;; No. Of Pins = 608
Manufacturer
Zarlink Semiconductor
Datasheet
Data Sheet
10.0
This chapter describes the data paths for all bytes transmitted and received with the H.110 interface.
10.1
The TX TDM section of the chip takes bytes from the H.110 interface and writes them into circular buffers in
SSRAM A. To do so, the MT92220 uses the TX Channel Association Memory to decide which of the 1023 time slots
on the H.110 bus it wants to treat. Each entry in the TX Channel Association Memory associates a time slot with
either a PCM buffer or an HDLC stream; the chip can support up to 1023 PCM buffers or up to 512 HDLC streams,
or any combination of the two (two PCM buffers cost the same as 1 HDLC stream). Any of the 1023 time slots
supported can also be configured as Low Latency Loopback: this means that the time slot will simply be looped
back onto another time slot on the H.110 bus.
This is the format of the TX Channel Association Memory:
TX/RX TDM Data Paths
TX TDM Data Path
+0
+2
+4
+6
TX Channel Association Memory Entry
b 15
AS
b14
b13
Figure 72 - TX Channel Association Memory
81FF0h
81FF8h
80000h
80008h
b12
b11
b10
Zarlink Semiconductor Inc.
b9
b8
Entry 1022
Entry 1023
Entry 0
Entry 1
b7
Stream/Buffer Tag
TSST [11:0]
Link to Next Entry
b6
b5
b4
b3
b2
b1
b0
MT92220
135

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