MT58L128L18F Micron Semiconductor Products, Inc., MT58L128L18F Datasheet - Page 12

• Manufacturer Part Number: MT58L128L18F
• Description: 2Mb Syncburst SRAM, 3.3V Vdd, 3.3V or 2.5V I/O, Flow-Through,
• Manufacturer: Micron Semiconductor Products, Inc.

NOT RECOMENDED FOR NEW DESIGNS
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 1) (0°C ≤ T
NOTE: 1. Test conditions as specified with the output loading shown in Figure 1 for 3.3V I/O (V
2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM
MT58L128L18F_C.p65 – Rev. C, Pub. 11/02
DESCRIPTION
Clock
Clock cycle time
Clock frequency
Clock HIGH time
Clock LOW time
Output Times
Clock to output valid
Clock to output invalid
Clock to output in Low-Z
Clock to output in High-Z
OE# to output valid
OE# to output in Low-Z
OE# to output in High-Z
Setup Times
Address
Address status (ADSC#, ADSP#)
Address advance (ADV#)
Byte write enables
(BWa#-BWd#, GW#, BWE#)
Data-in
Chip enable (CE#)
Hold Times
Address
Address status (ADSC#, ADSP#)
Address advance (ADV#)
Byte write enables
(BWa#-BWd#, GW#, BWE#)
Data-in
Chip enable (CE#)
2. Measured as HIGH above V
3. This parameter is measured with the output loading shown in Figure 2 for 3.3V I/O and Figure 4 for 2.5V I/O.
4. This parameter is sampled.
5. Transition is measured ±500mV from steady state voltage.
6. Refer to Technical Note TN-58-09, “Synchronous SRAM Bus Contention Design Considerations,” for a more thorough
7. OE# is a “Don’t Care” when a byte write enable is sampled LOW.
8. A READ cycle is defined by byte write enables all HIGH or ADSP# LOW for the required setup and hold times. A WRITE
9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK
Figure 3 for 2.5V I/O (V
discussion on these parameters.
cycle is defined by at least one byte write enable LOW and ADSP# HIGH for the required setup and hold times.
when either ADSP# or ADSC# is LOW and chip enabled. All other synchronous inputs must meet the setup and hold
times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at
each rising edge of CLK when either ADSP# or ADSC# is LOW to remain enabled.
A
≤ +70°C; V
DD
DD
Q = +2.5V +0.4V/-0.125V).
= +3.3V +0.3V/-0.165V)
IH
and LOW below V
SYMBOL
t
t
t
t
t
t
t
t
KQHZ
t
OEHZ
ADSH
KQLZ
ADSS
t
t
OELZ
t
t
AAH
t
KQX
OEQ
t
t
t
t
t
AAS
f
t
t
t
CEH
CES
WH
WS
KH
KQ
AH
DH
KC
AS
DS
KF
KL
MIN
8.0
1.8
1.8
1.5
1.5
1.8
1.8
1.8
1.8
1.8
1.8
0.5
0.5
0.5
0.5
0.5
0.5
IL
0
.
-6.8
12
FLOW-THROUGH SYNCBURST SRAM
MAX
125
6.8
3.8
3.8
3.8
MIN
8.8
1.9
1.9
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
0
-7.5
2Mb: 128K x 18, 64K x 32/36
MAX
113
Micron Technology, Inc., reserves the right to change products or specifications without notice.
7.5
4.2
4.2
4.2
MIN
10.0
1.9
1.9
3.0
1.5
2.0
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
0
-8.5
MAX
100
8.5
5.0
5.0
5.0
DD
Q = +3.3V +0.3V/-0.165V) and
MIN
4.0
4.0
3.0
1.5
2.5
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
0.5
15
0
-10
MAX UNITS NOTES
10.0
5.0
5.0
5.0
66
©2002, Micron Technology, Inc.
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3, 4, 5, 6
3, 4, 5, 6
3, 4, 5, 6
3, 4, 5, 6
8, 9
8, 9
8, 9
8, 9
8, 9
8, 9
8, 9
8, 9
8, 9
8, 9
8, 9
8, 9
2
2
3
7