MT57V256H36P Micron Semiconductor Products, Inc., MT57V256H36P Datasheet - Page 18

• Manufacturer Part Number: MT57V256H36P
• Description: 9Mb DDR SRAM 2.5V Vdd, HSTL Pipelined
• Manufacturer: Micron Semiconductor Products, Inc.

BYPASS
tion register and the TAP is placed in a Shift-DR state, the
bypass register is placed between TDI and TDO. The
advantage of the BYPASS instruction is that it shortens
the boundary scan path when multiple devices are con-
nected together on a board.
TAP AC ELECTRICAL CHARACTERISTICS
(Notes 1, 2) (+20°C
NOTE: 1.
256K x 36 2.5V V
MT57V256H36P_5.p65 – Rev. 5, Pub. 5/02
DESCRIPTION
Clock
Clock cycle time
Clock frequency
Clock HIGH time
Clock LOW time
Output Times
TCK LOW to TDO unknown
TCK LOW to TDO valid
TDI valid to TCK HIGH
TCK HIGH to TDI invalid
Setup Times
TMS setup
Capture setup
Hold Times
TMS hold
Capture hold
When the BYPASS instruction is loaded in the instruc-
2. Test conditions are specified using the load in Figure 4.
DD
t
, HSTL, Pipelined DDR SRAM
CS and
t
CH refer to the setup and hold time requirements of latching data from the boundary scan register.
Test Mode Select
T
Test Data-Out
J
Test Data-In
Test Clock
+100°C, +2.4V
(TDO)
(TMS)
(TCK)
(TDI)
1
V
DD
t MVTH
t DVTH
+2.6V)
TAP TIMING
2
t THTL
t THMX
t THDX
2.5V V
18
t
TLTH
RESERVED
served for future use. Do not use these instructions.
3
DD
These instruction are not implemented but are re-
t THTH
Micron Technology, Inc., reserves the right to change products or specifications without notice.
, HSTL, PIPELINED DDR SRAM
DON’T CARE
4
t TLOX
SYMBOL
t TLOV
t
t
t
t
t
t
t
t
t
MVTH
THMX
THTH
DVTH
THDX
TLOX
TLOV
THTL
TLTH
t
t
f
CH
TF
CS
5
UNDEFINED
MIN
100
40
40
10
10
10
10
10
10
0
6
256K x 36
MAX
©2002, Micron Technology, Inc.
10
20
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns