MT54V512H18E Micron Semiconductor Products, Inc., MT54V512H18E Datasheet - Page 12

• Manufacturer Part Number: MT54V512H18E
• Description: 9Mb QDR SRAM, 2.5V Vdd, HSTL , 4-Word Burst,
• Manufacturer: Micron Semiconductor Products, Inc.

Notes
512K x 18, 2.5V V
MT54V512H18E_16_A.fm - Rev 10/02
10. Typical values are measured at V
1. Outputs
2. Outputs are impedance-controlled. I
3. All voltages referenced to V
4. Overshoot:
5. AC load current is higher than the shown DC val-
6. For higher V
7. HSTL outputs meet JEDEC HSTL Class I and Class
8. To maintain a valid level, the transitioning edge of
9. I
(V
2)/(RQ/5) for values of 175 W £ RQ £ 350 W .
Undershoot: V
Power-up:
and V
During normal operation, V
V
widths less than
rates less than
ues. AC I/O curves are available upon request.
product information.
II standards.
the input must:
a. Sustain a constant slew rate from the current AC
b. Reach at least the target AC level
c. After the AC target level is reached, continue to
increases with faster cycle times. I
with faster cycle times and greater output loading.
Typical value is measured at 7.5ns cycle time.
1.5V, and temperature = 25°C.
DD
DD
V
maintain at least the target DC level, V
V
DD
level through the target AC level, V
IH
IH
. R# and W# signals may not have pulse
DD
is specified with no output current and
Q/2)/(RQ/5) for values of 175 W £ RQ £ 350 W .
(
(
DD
, HSTL, QDRb4 SRAM
AC
DC
Q £ 1.4V for t £ 200ms
)
)
are
V
V
DD
t
IH
IH
IL
KHKH (MIN).
impedance-controlled.
(
Q voltages, contact factory for
(
t
AC
AC
KHKL (MIN) or operate at cycle
£ V
) ³ -0.5V for t £
) £ V
DD
Q + 0.3V and V
DD
SS
+ 0.7V for t £
DD
(GND).
Q must not exceed
DD
t
DD
KHKH/2
=2.5V, V
OL
Q increases
DD
= (V
t
IL
KHKH/2
IL
|I
(
OH
(
AC
£ 2.4V
0.16µm Process
DD
DC
DD
|
) or
) or
Q =
Q/
=
12
11. Operating supply currents and burst mode cur-
12. NOP currents are valid when entering NOP after
13. Average I/O current and power is provided for
14. This parameter is sampled.
15. Average thermal resistance between the die and
16. Junction temperature is a function of total device
17. Control input signals may not be operated with
18. Test conditions as specified with the output load-
19. If C, C# are tied HIGH, then K, K# become the ref-
20. Transition is measured ±100mV from steady state
21.
22. This is a synchronous device. All addresses, data,
rents are calculated with 50 percent READ cycles
and 50 percent WRITE cycles.
all pending READ and WRITE cycles are com-
pleted.
informational purposes only and is not tested.
Calculation assumes that all outputs are loaded
with C
of outputs toggle at each transition (for example,
n = 18 for x36), C
equations: Average I/O Power as dissipated by the
SRAM is:
P = 0.5 × n x f x V
n x f x V
the case top surface per MIL SPEC 883 Method
1012.1.
power dissipation and device mounting environ-
ment. Measured per SEMI G38-87.
pulse widths less than
ing as shown in Figure 5, unless otherwise noted.
erences for C, C# timing parameters.
voltage.
t
and temperature.
and control lines must meet the specified setup
and hold times for all latching clock edges.
2.5V V
CHQXI is greater than
Micron Technology, Inc., reserves the right to change products or specifications without notice.
L
DD
(in farads), f = input clock frequency, half
Q x (C
DD
, HSTL, QDRb4 SRAM
DD
L
O
+ C
= 6pF, V
Q
2
O
x (C
t
).
t
KHKL (MIN).
CHQZ at any given voltage
L
DD
+ 2C
Q = 1.5V and uses the
O
512K x 18
). Average I
©2002, Micron Technology Inc.
ADVANCE
DD
Q =