MT28F002B5 Micron Semiconductor Products, Inc., MT28F002B5 Datasheet - Page 12

• Manufacturer Part Number: MT28F002B5
• Description: 2Mb Smart 5 Boot Block Flash Memory
• Manufacturer: Micron Semiconductor Products, Inc.

COMMAND EXECUTION
ent operational modes. Each mode allows specific op-
erations to be performed. Several modes require a
sequence of commands to be written before they are
reached. The following section describes the properties
of each mode, and Table 3 lists all command sequences
required to perform the desired operation.
READ ARRAY
upon power-up and after a RESET. If the device is in any
other mode, READ ARRAY (FFH) must be given to
return to the array read mode. Unlike the WRITE SETUP
command (40H), READ ARRAY does not need to be
given before each individual read access.
IDENTIFY DEVICE
to enter the identify device mode. While the device is
in this mode, any READ will produce the device ID
when A0 is HIGH and manufacturer compatibility ID
when A0 is LOW. The device will remain in this mode
until another command is given.
NOTE: 1. Must follow WRITE or ERASE CONFIRM commands to the CEL in order to enable flash array READ cycles.
2Mb Smart 5 Boot Block Flash Memory
F50.p65 – Rev. 1/00
COMMANDS
READ ARRAY
IDENTIFY DEVICE
READ STATUS REGISTER
CLEAR STATUS REGISTER
ERASE SETUP/CONFIRM
ERASE SUSPEND/RESUME
WRITE SETUP/WRITE
ALTERNATE WORD/BYTE
WRITE
Commands are issued to bring the device into differ-
IDENTIFY DEVICE (90H) may be written to the CEL
The array read mode is the initial state of the device
2. IA = Identify Address: 00H for manufacturer compatibility ID; 01H for device ID.
3. ID = Identify Data.
4. SRD = Status Register Data.
5. On x16 (X00) devices BA = Block Address (A12-A16), on x8 (00X) devices BA = Block Address (A13-A17).
6. Addresses are “Don’t Care” in first cycle but must be held stable.
7. WA = Address to be written; WD = Data to be written to WA.
CYCLES
REQ’D OPERATION ADDRESS DATA OPERATION ADDRESS DATA
BUS
1
3
2
1
2
2
2
2
Command Sequences
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
SMART 5 BOOT BLOCK FLASH MEMORY
Table 3
CYCLE
12
1ST
X
X
X
X
X
X
X
X
WRITE SEQUENCE
the array. WRITE SETUP (40H or 10H) is given in the
first cycle. The next cycle is the WRITE, during which
the write address and data are issued and V
to V
RP# pin be brought to V
brought HIGH at the same time V
The ISM will now begin to write the word or byte. V
must be held at V
(SR7 = 1).
bit (SR7) will be at “0,” and the device will not respond
to any commands. Any READ operation will produce
the status register contents on DQ0-DQ7. When the
ISM status bit (SR7) is set to a logic 1, the WRITE has
been completed, and the device will go into the status
register read mode until another command is given.
aborted except by a RESET or by powering down the
part. Doing either during a WRITE will corrupt the data
being written. If only the WRITE SETUP command has
been given, the WRITE may be nullified by performing
Two consecutive cycles are needed to write data to
While the ISM executes the WRITE, the ISM status
After the ISM has initiated the WRITE, it cannot be
PPH
Micron Technology, Inc., reserves the right to change products or specifications without notice.
. Writing to the boot block also requires that the
B0H
90H
70H
50H
20H
40H
10H
FFH
WRITE
WRITE
WRITE
WRITE
READ
READ
PPH
until the WRITE is completed
CYCLE
HH
2ND
WA
WA
BA
IA
or that the WP# pin be
X
X
PP
is brought to V
D0H
D0H
SRD
WD
WD
©2000, Micron Technology, Inc.
ID
PP
is brought
2Mb
NOTES
2, 3
5, 6
6, 7
6, 7
1
4
PPH
PP
.