MT28F002B5 Micron Semiconductor Products, Inc., MT28F002B5 Datasheet - Page 11

• Manufacturer Part Number: MT28F002B5
• Description: 2Mb Smart 5 Boot Block Flash Memory
• Manufacturer: Micron Semiconductor Products, Inc.

COMMAND SET
MT28F002B5 and MT28F200B5 incorporate an ISM
that controls all internal algorithms for the WRITE and
ERASE cycles. An 8-bit command set is used to control
the device. Details on how to sequence commands are
provided in the Command Execution section. Table 1
lists the valid commands.
ISM STATUS REGISTER
check for WRITE or ERASE completion or any related
errors. During or following a WRITE, ERASE or ERASE
SUSPEND, a READ operation will output the status
register contents on DQ0-DQ7 without prior com-
mand. While the status register contents are read, the
outputs will not be updated if there is a change in the
2Mb Smart 5 Boot Block Flash Memory
F50.p65 – Rev. 1/00
STATUS
SR0-2
BIT #
SR7
SR6
SR5
SR4
SR3
To simplify writing of the memory blocks, the
The 8-bit ISM status register (see Table 2) is polled to
STATUS REGISTER BIT
ISM STATUS
1 = Ready
0 = Busy
ERASE SUSPEND STATUS
1 = ERASE suspended
0 = ERASE in progress/completed
ERASE STATUS
1 = BLOCK ERASE error
0 = Successful BLOCK ERASE
WRITE STATUS
1 = WORD/BYTE WRITE error
0 = Successful WORD/
V
1 = No V
0 = V
RESERVED
PP
BYTE WRITE
STATUS
PP
present
PP
voltage detected
Status Register
by a CLEAR STATUS REGISTER command or after a RESET.
DESCRIPTION
The ISMS bit displays the active status of the state machine during
WRITE or BLOCK ERASE operations. The controlling logic polls this
bit to determine when the erase and write status bits are valid.
Issuing an ERASE SUSPEND places the ISM in the suspend mode
and sets this and the ISMS bit to “1.” The ESS bit will remain “1” until
an ERASE RESUME is issued.
ES is set to “1” after the maximum number of ERASE cycles is
executed by the ISM without a successful verify. ES is only cleared
WS is set to “1” after the maximum number of WRITE cycles is
executed by the ISM without a successful verify. WS is only cleared
by a CLEAR STATUS REGISTER command or after a RESET.
V
continuously, nor does it indicate a valid V
sampled for 5V after WRITE or ERASE CONFIRM is given. V
cleared by CLEAR STATUS REGISTER or by a RESET.
Reserved for future use.
PP
SMART 5 BOOT BLOCK FLASH MEMORY
S detects the presence of a V
Table 2
11
ISM status unless OE# or CE# is toggled. If the device is
not in the write, erase, erase suspend or status register
read mode, READ STATUS REGISTER (70H) can be
issued to view the status register contents.
ISM and erase suspend status bits are reset by the ISM.
The erase, write and V
using CLEAR STATUS REGISTER. If the V
(SR3) is set, the CEL will not allow further WRITE or
ERASE operations until the status register is cleared.
This allows the user to choose when to poll and clear
the status register. For example, the host system may
perform multiple BYTE WRITE operations before check-
ing the status register instead of checking after each
individual WRITE. Asserting the RP# signal or powering
down the device will also clear the status register.
All of the defined bits are set by the ISM, but only the
Micron Technology, Inc., reserves the right to change products or specifications without notice.
PP
voltage. It does not monitor V
PP
status bits must be cleared
PP
voltage. The V
©2000, Micron Technology, Inc.
PP
PP
PP
S must be
pin is
status bit
2Mb
PP