MT28C3224P18 Micron Semiconductor Products, Inc., MT28C3224P18 Datasheet - Page 16

• Manufacturer Part Number: MT28C3224P18
• Description: 2 Meg X 16 Page Flash, 256K X 16 SRAM Combo Memory, 66-ball Fbga
• Manufacturer: Micron Semiconductor Products, Inc.

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory
MT28C3224P20_4.p65 – Rev. 4, Pub. 10/02
STATUS
BIT #
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
WSMS
7
STATUS REGISTER BIT
WRITE STATE MACHINE STATUS (WSMS) Check write state machine bit first to determine word
1 = Ready
0 = Busy
ERASE SUSPEND STATUS (ESS)
1 = BLOCK ERASE Suspended
0 = BLOCK ERASE in
ERASE STATUS (ES)
1 = Error in Block Erasure
0 = Successful BLOCK ERASE
PROGRAM STATUS (PS)
1 = Error in PROGRAM
0 = Successful PROGRAM
V
1 = V
0 = V
PROGRAM SUSPEND STATUS (PSS)
1 = PROGRAM Suspended
0 = PROGRAM in Progress/Completed
BLOCK LOCK STATUS (BLS)
1 = PROGRAM/ERASE Attempted on a
0 = No Operation to Locked Blocks
RESERVED FOR FUTURE
ENHANCEMENT
PP
Progress/Completed
STATUS (V
Locked Block; Operation Aborted
PP
PP
= OK
Low Detect, Operation Abort
ESS
6
PP
S)
ES
5
Status Register Bit Definition
PS
4
When ERASE SUSPEND is issued, WSM halts execution and
“1” until an ERASE RESUME command is issued.
When this bit is set to “1,” WSM has applied the maximum
number of erase pulses to the block and is still unable to
verify successful block erasure.
When this bit is set to “1,” WSM has attempted but failed to
program a word.
The V
of the V
When PROGRAM SUSPEND is issued, WSM halts execution
“1” until a PROGRAM RESUME command is issued.
If a PROGRAM or ERASE operation is attempted to one of
the locked blocks, this is set by the WSM. The operation
specified is aborted, and the device is returned to read status
This bit is reserved for future.
program or block erase completion, before checking
program or erase status bits.
sets both WSMS and ESS bits to “1.” ESS bit remains set to
after the program or erase command sequences have been
entered and informs the system if V
also checked before the PROGRAM/ERASE operation is
verified by the WSM. A factory option allows PROGRAM or
ERASE at 0V, in which case SR3 is held at “0.”
and sets both WSM and PSS bits to “1.” PSS bit remains set to
mode.
Table 7
16
256K x 16 SRAM COMBO MEMORY
PP
PP
status bit does not provide continuous indication
level. The WSM interrogates the V
V
PP
3
S
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2 MEG x 16 PAGE FLASH
DESCRIPTION
PSS
2
PP
< 0.9V. The V
BLS
1
PP
level only
©2002, Micron Technology, Inc.
PP
level is
R
0