WM8148 Wolfson Microelectronics Ltd., WM8148 Datasheet - Page 38

• Manufacturer Part Number: WM8148
• Description: WM8148 : 12-BIT/12 MSPS Ccd/cis Analogue Front End/digitiser
• Manufacturer: Wolfson Microelectronics Ltd.

WM8148
APPLICATIONS RECOMMENDATIONS
INTRODUCTION
PCB LAYOUT
TYPICAL APPLICATIONS DIAGRAMS
WOLFSON MICROELECTRONICS LTD
The WM8148 is a mixed signal device, therefore careful PCB layout is required. The following section
contains PCB layout guidelines, which are recommended for optimal performance from the WM8148,
and some typical applications circuits.
1)
2)
3)
4)
5)
6)
CCDs are available in four basic types that are all compatible with the WM8148.
Each of these applications is outlined in this section.
The output from a CCD sensor usually has a high impedance and must therefore be buffered
as close to the sensor as possible. The sensor manufacturers’ datasheets specify the buffer circuit
to use.
Initially, the designer must decide if CDS and Reset Level Clamping is to be used. The WM8148
supports both of these functions and Wolfson recommend using both CDS and pixel-by-pixel
clamping for optimal performance. In this case a low value a.c. coupling capacitor is required
between the sensor and the WM8148. Experiments have shown that a 100pF capacitor is the
optimum value to use, however this may vary for particular applications depending on speed of
operation and PCB layout.
Monochrome single output.
Monochrome odd-even output.
Colour 3 output.
Colour 6 output.
Use separate analogue and digital power and ground planes. The analogue and digital ground
planes should be connected as close as possible to, or underneath, the WM8148.
Place all supply decoupling capacitors as close as possible to their respective supply pins and
provide a low impedance path from the capacitors to the appropriate ground.
Avoid noise on AGND (in particular on pins 30, 35 and 40).
Avoid noise on reference pins VRT, VRB and VRX. Place the decoupling capacitors as close as
possible to these pins and provide a low impedance path from the capacitors to analogue
ground.
Input signals should be screened from each other and from other sources of noise to avoid
cross talk and interference.
Minimise load capacitance on digital outputs. Capacitive loads of greater than 20pF will degrade
performance. Use buffers if necessary and keep tracks short.
PD Rev 4.0 April 1999
Production Data
38