WM8148 Wolfson Microelectronics Ltd., WM8148 Datasheet - Page 2

• Manufacturer Part Number: WM8148
• Description: WM8148 : 12-BIT/12 MSPS Ccd/cis Analogue Front End/digitiser
• Manufacturer: Wolfson Microelectronics Ltd.

WM8148
PIN CONFIGURATION
PIN DESCRIPTION
WOLFSON MICROELECTRONICS LTD
PIN
10
11
12
13
14
15
16
17
18
19
20
21
D G N D 3
D G N D 1
D V D D 1
A G N D 5
A V D D 4
1
2
3
4
5
6
7
8
9
V S M P
M C L K
R L C
O P 0
O P 1
O P 2
O P 3
DVDD1
DGND3
AGND5
DGND1
DVDD2
AVDD4
VSMP
NAME
MCLK
OP10
OP11
RLC
OP0
OP1
OP2
OP3
OP4
OP5
OP6
OP7
OP8
OP9
1 0
1 1
1 2
1
2
4
5
6
7
8
9
3
4 8
1 3 1 4 1 5
4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8
1 6 1 7 1 8 1 9 2 0 2 1 2 2
Digital output
Digital output
Digital output
Digital output
Digital input
Digital input
Digital IO
Digital IO
Digital IO
Digital IO
Digital IO
Digital IO
Digital IO
Digital IO
Digital IO
Ground
Ground
Ground
Supply
Supply
Supply
TYPE
2 3
DESCRIPTION
Digital supply (3.3V to 5V) for digital inputs and SDO.
Selects whether reset level clamp is applied, active high. If RLC is required on every
pixel then this pin can be tied high.
Analogue supply (5V).
Digital ground (0V).
Master clock. This clock is applied at N times the input pixel rate (N = 12, 8, 6, or
4 dependent on input sampling mode). MCLK is divided internally by N to generate
internal clocks and to provide the clock source for digital logic.
Analogue ground (0V).
Video sample synchronisation pulse. This pin may be either an input (default) or output.
Input: This signal is pulsed externally
to synchronise the WM8148’s video
input sample instant and the N-phase
internal clock to CCD clocks and
interface bus timing.
Digital ground (0V) for output drivers.
12-bit signal data output bus. Data is output MSB on OP[11] and LSB on pin OP[0].
See description of pins 14-21 for mode definitions.
Digital supply (3.3V-5V) for Digital IO pins and OP0 to OP3
12-bit bi-directional data bus. On pins OP[4] to OP[11], signal data is output if OEB = 0
and register write data is input if OEB = 1.
There are five main modes:
3 7
2 4
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
Hi-Z: when OEB = 1
Output 12-bit: twelve bit signal data output from bus
Output 8-bit muxed: signal data output on OP[11:4] at 2
Input 8-bit: register write data input on OP[11:4]
Output 8-bit: register readback data output on OP[11:4]
R I N P
A G N D 1
O V R D
V R L C
V R X
V R T
A G N D 3
V R B
A V D D 2
A V D D 3
D G N D 4
A G N D 4
ORDERING INFORMATION
XWM8148CFT/V
DEVICE
Output: This signal is pulsed internally to
flag the video input sample instant, to allow
the CCD clocks and interface bus to be
synchronised to the WM8148.
TEMP. RANGE
0 to 70
o
C
ADC conversion rate
PD Rev 4.0 April 1999
thick body TQFP
48-pin 1mm
Production Data
PACKAGE
2