WM8148 Wolfson Microelectronics Ltd., WM8148 Datasheet - Page 17

• Manufacturer Part Number: WM8148
• Description: WM8148 : 12-BIT/12 MSPS Ccd/cis Analogue Front End/digitiser
• Manufacturer: Wolfson Microelectronics Ltd.

WM8148
RESET LEVEL CLAMPING (RLC)
WOLFSON MICROELECTRONICS LTD
If the sensor output voltage is within the input range of the WM8148, the sensor may be d.c. coupled
into the WM8148 either directly or via a buffer. If the output from the sensor is outside the input range
of the WM8148, the signal has to be connected via a capacitor, C
be defined on the WM8148 side of the capacitor (at RINP).
Setting of the d.c. bias conditions is best performed by Reset-Level Clamping, activated by pin RLC.
Reset-Level Clamping is compatible with both CDS and non-CDS operating modes. A typical
configuration is shown in Figure 16.
When the clamp pulse, CL, is active, the voltage on the WM8148 side of C
equal to the VRLC voltage, V
initially remain at V
of C
incoming signal (CDS operation) or the VRLC pin (non-CDS operation).
Figure 17 demonstrates the case of a typical CCD waveform, with CL applied during the reset period.
Figure 17 Relationship of RLC pin, MCLK and VSMP to Internal Clamp Pulse, CL
The input signal applied to the RLC pin is sampled on the positive edge of MCLK that occurs during
each VSMP pulse. The sampled level, high (or low) controls the presence (or absence) of the internal
CL pulse on the next reset level. The position and duration of CL is adjustable by control bits
RESREF[3:0] and SMALL.
Figure 16 Reset-Level Clamping Circuitry
Input Video
IN
will couple through C
M C L K
V S M P
EXTERNAL VRLC
R L C
C L
r,g,b
1
C
VRLC
IN
VRLC
RINP
Programmable Delay
, but any subsequent variation in sensor voltage appearing at the sensor side
IN
VRLC
to RINP. Switch 2 determines whether the R
X
, by switch 1. When the CL pulse turns off, the RINP voltage will
1
RLC on this pixel
RLC
CL
X
2
TIMING CONTROL
RLC DAC
RLC
4-BIT
S/H
MODE[0]
r,g,b
R
S
CDS
MCLK
0
S/H
V
S
VSMP
X
IN
INPUT SAMPLING
BLOCK FOR RED
, and the d.c. bias conditions must
CHANNEL
+
-
+
No RLC on this pixel
X
IN
S
, at RINP, will be forced
level is taken from the
FROM CONTROL
INTERFACE
TO OFFSET DAC
FROM CONTROL
INTERFACE
PD Rev 4.0 April 1999
0
Production Data
r,g,b
X
17