WM8148 Wolfson Microelectronics Ltd., WM8148 Datasheet - Page 15

• Manufacturer Part Number: WM8148
• Description: WM8148 : 12-BIT/12 MSPS Ccd/cis Analogue Front End/digitiser
• Manufacturer: Wolfson Microelectronics Ltd.

WM8148
DEVICE DESCRIPTION
INTRODUCTION
INPUT SAMPLING
WOLFSON MICROELECTRONICS LTD
The WM8148 samples up to three analogue inputs simultaneously, conditions these signals and
converts each resulting analogue signal to a 12-bit digital word.
A block diagram is shown on page 1. Each of the three input channels consists of an Input Sampling
block (CDS/RLC), an 8-bit programmable Offset DAC, and a 6-bit Programmable Gain Amplifier
(PGA). The outputs from the three channels are multiplexed into a 12-bit ADC. The digital output from
the ADC is presented on a 12-bit wide bi-directional bus.
A high-speed (up to 48MHz) master clock, MCLK, and a per-pixel synchronisation pulse, VSMP, drive
a shared Timing Control block to generate input sampling signals and other internal clocks.
Alternatively the device can operate from MCLK only, outputting VSMP synchronisation pulses to the
rest of the system.
An internal reference provides buffered voltages VRT, VRB and VRX. A 4-bit DAC (RLC DAC)
provides a programmable buffered voltage at pin VRLC for use as an input signal reference level or
an input clamp voltage.
The operation of the device is controlled by internal control registers, which can be read from and
written to via a Digital Management Interface (DMI) in either serial or parallel mode.
Figure 14 shows the configuration of the Input Sampling Block for the red channel. (The green and
blue channels are the same.)
Figure 14 Input Sampling Block – Configuration for Red Channel
This block contains switches to perform Reset Level Clamping (RLC) and Correlated Double
Sampling (CDS). Sample/Hold blocks sample the video and reset/reference levels of the input
waveform, and pass the difference signal on to the rest of the channel. Internal clocks V
define the timing of the sampling of the video signal and the reset/reference level respectively. When
enabled by control input pin RLC, internal signal CL clamps the input pin RINP to the voltage on pin
VRLC, which is driven either externally or from the 4-bit RLC DAC.
The detailed timing of the internal clock signals CL, V
controlled by the Timing Control block as programmed via the Digital Management Interface (DMI).
VRLC
RINP
RLC
CL
TIMING CONTROL
RLC DAC
RLC
4-BIT
S/H
MODE[0]
R
S
CDS
MCLK
S/H
V
S
VSMP
S
, and R
INPUT SAMPLING
BLOCK FOR RED
+
-
+
CHANNEL
S,
with respect to VSMP and MCLK, is
From Control Interface
From Control Interface
To Offset DAC
PD Rev 4.0 April 1999
Production Data
S
and R
15
S