WM8148 Wolfson Microelectronics Ltd., WM8148 Datasheet - Page 23

• Manufacturer Part Number: WM8148
• Description: WM8148 : 12-BIT/12 MSPS Ccd/cis Analogue Front End/digitiser
• Manufacturer: Wolfson Microelectronics Ltd.

WM8148
OUTPUT ENABLE
POWER MANAGEMENT
WOLFSON MICROELECTRONICS LTD
REGISTER READ-BACK
Figure 25 Parallel Interface Register Read-back
Register read-back is initiated by writing the 6-bit address (a5, 1, a3, a2, a1, a0) into OP[9:4] by
pulsing the STB pin low. Note that a4 = 1 and pins RNW and DNA are low. When RNW and DNA are
high and STB is strobed again, the contents (d7, d6, d5, d4, d3, d2, d1, d0) of the corresponding
register (a5, 0, a3, a2, a1, a0) will be output on OP[11:4], LSB on pin OP[4]. Until STB is pulsed low,
the current contents of the ADC (shown as Normal Output Data) will be present on OP[11:4].
When high, pin OEB makes pins OP[11:0] Hi-Z regardless of other pin settings. Therefore when the
WM8148 is outputting normal ADC data, or during register read, pin OEB must be set to ‘0’. During
register write, pin RNW set to ‘0’ ensures that the outputs are Hi-Z, therefore pin OEB is ‘don’t care’.
Table 4 shows the state of pins OP[11:0] for possible settings of OEB, RNW and STB.
Table 4 State of OP[11:0] During Register Read/Write
Power management for the WM8148 is performed via the DMI. The device can be powered on or off
completely by the control bit EN. Alternatively, when control bit SELEN is high, only blocks selected
by further control bits SENBL[7:0] are powered up. This allows the user to optimise power dissipation
in certain modes, or to define intermediate standby modes to allow a quicker recovery into a fully
active state.
Table 5 Power Down control
Control bit RLCEXT is used to disable the RLC DAC, regardless of EN or SENBL[7:0]. If this option is
taken, pin VRLC can be driven externally for reset level clamping.
One-channel and Two-channel sampling modes do not automatically power down unused PGAs, the
appropriate SENBL bits should be set during initialisation to save power. The WM8148 will still
operate normally if the unused blocks are not powered down.
All the internal registers maintain their previously programmed value in power down modes, and the
DMI inputs remain active.
OP[11:4]
EN
0
1
x
R N W
DNA
OEB
STB
1
0
0
x
Normal Output Data
Driven by WM8148
SELEN
0
0
1
RNW
x
0
1
1
Device completely powers down.
Device completely powers up.
Only blocks with respective SENBL bit high
go/remain active.
Hi-Z
Driven Externally
Address
STB
x
x
0
1
Hi-Z
Read register data
Read ADC data
OP[11:0]
Hi-Z
Hi-Z
Read Data
Normal Output Data
Driven by WM8148
PD Rev 4.0 April 1999
Production Data
23