ATA5423 ATMEL Corporation, ATA5423 Datasheet - Page 57

• Manufacturer Part Number: ATA5423
• Manufacturer: ATMEL Corporation

Figure 9-5.
4841A–RKE–02/05
Bit-check counter
RX_ACTIVE
Demod_Out
(Lim_min = 14, Lim_max = 24)
Timing Diagram During Bit Check
Bit check
Start-up mode
T
Startup_Sig_Proc
For the best noise immunity, use of a low span between T
This is achieved using a fixed frequency at a 50% duty cycle for the transmitter preburst: a
“11111...” or a “10101...” sequence in Manchester or Bi–phase is a good choice. A good com-
promise between sensitivity and susceptibility to noise regarding the expected edge–to–edge
time, t
±50% and then N
periods, the bit–check limits must be programmed according to the required span.
The bit–check limits are determined by means of the formula below:
Lim_min is defined by the bits Lim_min 0 to Lim_min 5 in control register 5.
Lim_max is defined by the bits Lim_max 0 to Lim_max 5 in control register 6.
Using the above formulas, Lim_min and Lim_max can be determined according to the required
T
minimum edge–to–edge time t
lower limit should be set to Lim_min
Lim_max = 63.
Figure
Lim_min = 14 and Lim_max = 24. The signal processing circuits are enabled during T
and T
that period. When the bit check becomes active, the bit–check counter is clocked with the cycle
T
Figure 9-5
limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In
page 58
check also fails if CV_Lim reaches Lim_max. This is illustrated in
Lim_min
XDCLK
0
Startup_Sig_Proc
ee
.
, T
9-5,
, is a time window of ±38%; to get the maximum sensitivity the time window should be
the bit check fails because the value CV_Lim is lower than the limit Lim_min. The bit
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 101112131415161718 1 2 3 4 5 6 7 8 9 10 11
Lim_max
shows how the bit check proceeds if the bit–check counter value CV_Lim is within the
Figure
and T
Bit–check
. The output of the ASK/FSK demodulator (Demod_Out) is undefined during
T
XDCLK
9-6, and
XDCLK
6. Using preburst patterns that contain various edge–to–edge time
. The time resolution defining T
Figure 9-7
ee
1/2 Bit
is defined in the section
ATA5423/25/28/29 [Preliminary]
Bit-check mode
illustrate the bit check for the bit–check limits
T
Bit check ok
10. The maximum value of the upper limit is
Bit-check
T
T
Lim_min
Lim_max
Lim_min
1/2 Bit
“Receiving Mode” on page
Lim_min
= Lim_min
= (Lim_max –1)
and T
Figure 9-7 on page
and T
12131415 1 2 3 4
Bit check ok
Lim_max
Lim_max
T
XDCLK
1/2 Bit
is recommended.
is T
5 6 7
Figure 9-6 on
T
XDCLK
XDCLK
58.
Startup_PLL
59. The
. The
57