ATA5423 ATMEL Corporation, ATA5423 Datasheet - Page 44

• Manufacturer Part Number: ATA5423
• Manufacturer: ATMEL Corporation

7.5
44
Pin Tn
ATA5423/25/28/29 [Preliminary]
Table 7-22.
To switch the transceiver from OFF to IDLE mode, pin Tn must be set to “0” (maximum
0.2
sets pin N_RESET to low and switches on DVCC, AVCC and the power supply for external
devices VSOUT.
If V
sets the status bit STn to “1” and an interrupt is issued (T
After the voltage on pin VSOUT exceeds 2.3 V (typically) and the start–up time of the XTO is
elapsed, the output clock on pin CLK is available. Because the enabling of pin CLK is asynchro-
nous, the first clock cycle may be incomplete. N_RESET is set to high if V
(typically) and the XTO is settled.
Figure 7-2.
P_On_Aux
Status Bit
Power_On
Low_Batt
DVCC
V
DVCC, AVCC
(Status Register)
VS2
exceeds 1.5 V (typically) and the XTO is settled, the digital control logic is active and
N_RESET
) for at least T
VSOUT
CLK
Status Register (Continued)
Timing Pin Tn, Status Bit STn
STn
IRQ
Function
Indicates that the transceiver was woken up by pin PWR_ON (rising edge on pin
PWR_ON). During Power_On = 1, the bits VSOUT_EN and CLK_ON in control register 3
are set to “1”.
(see
Indicates that output voltage on pin VSOUT is too low
(V
(see
Indicates that the auxiliary supply voltage on pin VAUX is high enough to operate.
State transition:
a) OFF mode
b) IDLE mode (VSOUT = VS1)
Tn
VSOUT
(see
Figure 7-4 on page
Figure 7-5 on page
1.5 V (typ)
Mode
OFF
Figure 7-6 on page
V
< 2.38 V typically)
Thres_2
Tn_IRQ
= 2.38 V (typ)
T
Tn_IRQ
AUX mode (see
(see
IDLE
Mode
Figure
46)
47)
V
48)
Thres_1
7-2). The transceiver recognizes the negative edge,
= 2.3 V (typ)
Figure 5-2 on page
IDLE mode (VSOUT = V_REG2)
Tn_IRQ
).
32)
VSOUT
exceeds 2.38 V
4841A–RKE–02/05