ATA5423 ATMEL Corporation, ATA5423 Datasheet - Page 51
ATA5423
Manufacturer Part Number
ATA5423
Description
Manufacturer
ATMEL Corporation
Datasheet
1.ATA5423.pdf
(97 pages)
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8.8
Figure 8-7.
4841A–RKE–02/05
4–wire Serial Interface
SDO_TMDO
SDI_TMDI
Serial Timing
SCK
CS
T
SCK_setup1
X
X can be either V
Table 8-1.
The 4–wire serial interface consists of the Chip Select (CS), the Serial Clock (SCK), the Serial
Data Input (SDI_TMDI) and the Serial Data Output (SDO_TMDO). Data is transmitted/received
bit by bit in synchronization with the serial clock.
Note:
When CS is low and the transparent mode is inactive (T_MODE = 0), SDO_TMDO is in a high–
impedance state. When CS is low and the transparent mode is active (T_MODE = 1), the RX
data stream is available on pin SDO_TMDO.
Command
Read TX/RX data buffer
Write TX/RX data buffer
Read control/status register
Write control register
OFF command
Delete IRQ
Not used
Not used
X
T
T
If the output level on pin N_RESET is low, no data communication with the microcontroller is
possible.
Out_enable
CS_setup
T
Setup
iL
Command Structure
or V
MSB
iH
T
Hold
MSB
T
Cycle
T
X
Out_delay
MSB
Bit 7
0
0
0
0
1
1
1
1
ATA5423/25/28/29 [Preliminary]
MSB-1
Bit 6
0
0
1
1
0
0
1
1
MSB-1
Bit 5
0
1
0
1
0
1
0
1
X
Bit 4
A4
A4
X
X
X
X
x
x
LSB
T
SCK_setup2
Bit 3
A3
A3
X
X
X
X
x
x
X
Bit 2
T
T
A2
A2
SCK_hold
T
X
X
X
X
x
x
CS_disable
Out_disable
X
Bit 1
A1
A1
X
X
X
X
x
x
Bit 0
LSB
A0
A0
X
X
X
X
x
x
51
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