ATA5423 ATMEL Corporation, ATA5423 Datasheet - Page 56

• Manufacturer Part Number: ATA5423
• Manufacturer: ATMEL Corporation

9.1.4
9.1.5
Figure 9-3.
56
ATA5423/25/28/29 [Preliminary]
RX_ACTIVE
Bit–check Mode
Configuration of the Bit Check
Demod_Out
Bit check
Timing Diagram for Complete Successful Bit Check (Number of Checked Bits: 3)
Start-up mode
T
Startup_Sig_Proc
In bit–check mode the incoming data stream is examined to distinguish between a valid signal
from a corresponding transmitter and signals due to noise. This is done by subsequent time
frame checks where the distance between 2 signal edges are continuously compared to a pro-
grammable time window. The maximum count of this edge–to–edge test before the transceiver
switches to receiving mode is also programmable.
Assuming a modulation scheme that contains 2 edges per bit, two time frame checks verify one
bit. This is valid for Manchester, Bi–phase and most other modulation schemes. The maximum
count of bits to be checked can be set to 0, 3, 6 or 9 bits via the variable N
register 5. This implies 0, 6, 12 and 18 edge–to–edge checks, respectively. If N
higher value, the transceiver is less likely to switch to receiving mode due to noise. In the pres-
ence of a valid transmitter signal, the bit check takes less time if N
In RX polling mode, the bit–check time is not dependent on N
Figure 9-3
As seen in
the edge–to–edge time t
check limit T
T
Figure 9-4.
Lim_max
, the bit check will be terminated and the transceiver switches to sleep mode.
shows an example where 3 bits are tested successfully.
Figure
Lim_max
Demod_Out
Valid Time Window for Bit Check
1/2 Bit
9-4, the time window for the bit check is defined by two separate time limits. If
, the check will be continued. If t
1/2 Bit
ee
is in between the lower bit–check limit T
Bit-check mode
1/2 Bit
T
Bit-check
Bit check ok
T
T
Lim_min
Lim_max
1/2 Bit
t
ee
ee
1/2 Bit
1/f
is smaller than limit T
Sig
Bit–check
1/2 Bit
Bit–check
if no valid signal is present.
Lim_min
Receiving mode
is set to a lower value.
and the upper bit–
Lim_min
Bit–check
Bit–check
4841A–RKE–02/05
or exceeds
in control
is set to a