CMX649E3 CML Microcircuits, CMX649E3 Datasheet - Page 24
![no-image](/images/no-image-200.jpg)
CMX649E3
Manufacturer Part Number
CMX649E3
Description
ADM Codec
Manufacturer
CML Microcircuits
Datasheet
1.CMX649E3.pdf
(52 pages)
- Current page: 24 of 52
- Download datasheet (412Kb)
ADM Codec
Decode Bit
Clock Divider
(Bits 5 – 3)
Encode Bit
Clock Divider
(Bits 2 – 0)
The audio filter clock divider should be programmed to set the audio filter clock as near as possible to
256kHz, via selection of the XTAL frequency and the Filter Prescaler and Filter Divider settings.
The encoder and decoder ADM bit rate clocks should be programmed to the desired ADM bit rate or
PCM sample rate, multiplied by the interpolation/decimation setting of the PCM filter. The PCM filter can
be programmed to run at either 4x or 8x the PCM sample rate depending on the corresponding setting in
the encode/decode processors.
The encoder and decoder ADM bit rate clocks are further divided by a constant factor of 64 (unless the
PLL is enabled in which case the average is near 64 but can pull off slightly depending on the reference
source).
2002 CML Microsystems Plc
These bits control the decode bit clock divider.
These bits control the encode bit clock divider.
Bit 5
Bit 2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Bit 4
Bit 1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Bit 3
Bit 0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
24
Divider Ratio
Divider Ratio
1.000
2.000
2.250
2.625
3.000
3.125
3.375
3.500
1.000
2.000
2.250
2.625
3.000
3.125
3.375
3.500
CMX649
D/649/1
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