MB81ES171625 Fujitsu Media Devices Limited, MB81ES171625 Datasheet - Page 9

• Manufacturer Part Number: MB81ES171625
• Description: SINGLE DATA RATE I/F FCRAM Consumer/Embedded Application Specific Memory for SiP
• Manufacturer: Fujitsu Media Devices Limited

2. DQM Truth Table
V
n
Notes :
3. CKE Truth Table
V
n
*1 : CSUS command requires that at least one bank is active. Refer to “ STATE DIAGRAM”.
*2 : REF and SELF commands should be issued only after all banks have been precharged (PRE or PALL command).
*3 : SELF and PD commands should be issued only after the last read data have been appeared on DQ.
*4 : CKE should be held High during t
Notes: TBST,BME and DSE should be held Low.
Data Input/Output Enable
Data Input/Output Disable
Bank Active
Any
Clock
Suspend
Idle
Idle
Self Refresh Self-refresh Exit *
Idle
Power Down Power Down Exit
(Except Idle)
Current
state at current clock cycle, n 1
state at current clock cycle, n 1
Refer to “ STATE DIAGRAM”.
Valid, L
Valid, L
State
S16 should be held V
All commands assume no CSUS command on previous rising edge of clock.
All commands assumed to be valid state transition.
All inputs are latched on the rising edge of clock.
DQ
MB81ES171625; DQM
MB81ES173225; DQM
All commands assume no CSUS command on previous rising edge of clock.
All commands are assumed to be valid state transition.
All inputs are latched on the rising edge of clock.
TBST, BME and DSE should be held Low.
S16 should be held V
31
Logic Low, H
Logic Low, H
Clock Suspend Mode
Entry *
Clock Suspend
Continue *
Clock Suspend Mode Exit
Auto-refresh Command *
Self-refresh Entry *
Power Down Entry *
to DQ
Function
24
1
, respectively.
Function
1
Logic High, X
Logic High, X
IH
, and S32 should be held V
IH
4
, and S32 should be held V
0
0
, DQM
2,
and DQM
3
*
3
REFC
state at 1 clock cycle before n.
state at 1 clock cycle before n.
2
1
.
, DQM
SELFX
CSUS
mand
Com-
SELF
REF
1
PD
control DQ
either L or H,
either L or H,
2
and DQM
Command
MB81ES171625/173225-15-X
n-1 n
MASK
ENBL
H
H
H
H
H
L
L
L
L
L
L
CKE
7
H
H
H
H
H
H
L
L
L
L
L
to DQ
IL
3
.
control DQ
IL
XCS XRAS XCAS XWE BA
.
X
X
X
H
H
H
L
L
L
L
L
0
and DQ
H
H
H
X
X
X
X
X
X
L
L
n-1
H
H
7
to DQ
15
to DQ
X
X
X
H
X
H
X
H
X
L
L
CKE
0
, DQ
8
, respectively.
15
X
X
X
H
H
H
X
H
X
H
X
to DQ
X
X
n
X
X
X
X
X
X
X
X
X
X
X
8
, DQ
A
AP
23
X
X
X
X
X
X
X
X
X
X
X
10
to DQ
/
DQM
H
L
A
A
12
9
16
to A
, A
, and
X
X
X
X
X
X
X
X
X
X
X
11
0
,
9