MB81ES171625 Fujitsu Media Devices Limited, MB81ES171625 Datasheet - Page 8

• Manufacturer Part Number: MB81ES171625
• Description: SINGLE DATA RATE I/F FCRAM Consumer/Embedded Application Specific Memory for SiP
• Manufacturer: Fujitsu Media Devices Limited

8
MB81ES171625/173225-15-X
1. Command Truth Table
V
n
*1: NOP and DESL commands have the same effect on the part. At DESL command (XCS
*2: BST command is effective on every Burst Length. (BL
*3: READ, READA, WRIT and WRITA commands should be issued only after the corresponding bank has been
*4: ACTV command should be issued only after the corresponding bank has been precharged (PRE or PALL
*5: Required after power up. Refer to “17. Power-Up- Initialization” in “ FUNCTIONAL DESCRIPTION.”
*6: MRS command should be issued only after all banks have been precharged (PRE or PALL command) and DQ
Notes: All commands assumes no CSUS command on previous rising edge of clock.
Device Deselect *
No Operation *
Burst Stop*
Read *
Read with
Auto-precharge *
Write *
Write with
Auto-precharge *
Bank Active *
Precharge Single Bank *
Precharge All Banks *
Mode Register Set *
FUNCTIONAL TRUTH TABLE
are ignored, but hold the internal state. NOP command (XCS “L”, XRAS XCAS XWE “H”) is no effect on
device operation and the internal state continue.
activated (ACTV command) . Refer to “ STATE DIAGRAM”.
command) .
is in High-Z. Refer to “ STATE DIAGRAM”.
state at current clock cycle, n 1
Valid, L
3
3
All commands are assumed to be valid state transitions.
All inputs are latched on the rising edge of the clock.
TBST,BME and DSE should be held Low.
S16 should be held V
Function
2
4
Logic Low, H
1
3
3
1
5,
*
X16
X32
X16
X32
X16
X32
X16
X32
5
6
5
READA
WRITA
mand
READ
ACTV
Logic High, X
Com-
DESL
WRIT
PALL
NOP
MRS
IH
PRE
BST
, and S32 should be held V
state at 1 clock cycle before n.
n-1
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
CKE
n
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
either L or H,
XCS XRAS XCAS XWE
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
X
L
L
L
L
IL
1, 2, 4, 8, full column)
.
H
H
H
H
H
X
L
L
L
L
L
L
L
L
L
X
H
H
H
H
H
H
L
L
L
L
L
L
L
L
BA
X
X
X
V
V
V
V
V
V
V
V
V
V
X
L
A
AP
X
X
X
H
H
H
H
V
H
L
L
L
L
L
L
10
/
“H”) , all input signal
A
12
A
X
X
X
X
X
X
X
X
X
X
X
V
X
X
V
6
to
A5
X
X
X
V
X
V
X
V
X
V
X
V
X
X
V
A
A
4
X
X
X
V
V
V
V
V
V
V
V
V
X
X
V
to
0