MB81ES171625 Fujitsu Media Devices Limited, MB81ES171625 Datasheet - Page 13

no-image

MB81ES171625

Manufacturer Part Number
MB81ES171625
Description
SINGLE DATA RATE I/F FCRAM Consumer/Embedded Application Specific Memory for SiP
Manufacturer
Fujitsu Media Devices Limited
Datasheet
(Continued)
ABBREVIATIONS
*1: Entry may affect other bank.
*2: Illegal to the bank in specified state; entry may be legal to the bank specified by BA, depending on the state of
*3: Illegal if any bank is not idle.
*4: Must satisfy bus contention, bus turn around, and/or write recovery requirements.
*5: SELF command should be issued only after the last read data has been appeared on DQ.
*6: MRS command should be issued only when all DQ are in High-Z.
*7: NOP in precharging or idle state. PRE may affect to the bank specified BA and AP .
Notes: TBST,BME and DSE should be held Low.
Mode
Register
Setting
Current
L
RA
CA
that bank.
Refer to “11. READ Interrupted by WRITE (Example @ CL = 2, BL = 4)” and “12. WRITE to READ Timing
(Example @ CL = 1, BL = 4)” in “ TIMING DIAGRAMS.”
State
Logic Low, H
S16 should be held V
All entries in “4. Operation Command Table” assume that CKE was High during the proceeding clock
cycle and the current clock cycle.
Illegal means that the device operation and/or data-integrity are not guaranteed. If used, power up sequence
will be asserted after power shut down.
All commands assume no CSUS command on previous rising edge of clock.
All commands are assumed to be valid state transitions.
All inputs are latched on the rising edge of the clock.
Row Address
Column Address AP
XCS
H
L
L
L
L
XRAS XCAS
Logic High, X
X
H
H
H
L
BA
IH
, and S32 should be held V
Bank Address
X
H
H
X
L
Auto Precharge
either L or H
XWE
H
X
X
X
L
Addr
MB81ES171625/173225-15-X
X
X
X
X
X
IL
PALL/REF/SELF/
.
READ/READA/
WRIT/WRITA
ACTV/PRE/
Command
DESL
NOP
MRS
BST
Idle after t
Illegal
RSC
Function
13

Related parts for MB81ES171625