MB81ES171625 Fujitsu Media Devices Limited, MB81ES171625 Datasheet - Page 19

• Manufacturer Part Number: MB81ES171625
• Description: SINGLE DATA RATE I/F FCRAM Consumer/Embedded Application Specific Memory for SiP
• Manufacturer: Fujitsu Media Devices Limited

13. Auto-Refresh (REF)
14. Self-Refresh Entry (SELF)
Note : When the burst refresh method is used, a total of 2048 auto-refresh commands must be asserted within
15. Self-Refresh Exit (SELFX)
Note : When the burst refresh method is used, a total of 2048 auto-refresh commands must be asserted within 1
16. Mode Register Set (MRS)
17. Power-Up Initialization
Auto-refresh uses the internal refresh address counter. SDR I/F FCRAM Auto-refresh command (REF) generates
the Precharge command internally. All banks of SDR I/F FCRAM should be precharged prior to the Auto-refresh
command. The Auto-refresh command should also be asserted every 1.95 s or a total 2048 refresh commands
within a 4 ms period.
Self-refresh function provides automatic refresh by an internal timer as well as Auto-refresh and will continue
the refresh function until cancelled by SELFX.
Self-refresh is entered by applying an Auto-refresh command in conjunction with CKE
SDR I/F FCRAM enters the self-refresh mode, all inputs except for CKE will be “don’t care” (either logic high or
low level state) and outputs will be in High-Z state. During a self-refresh mode, CKE Low should be maintained.
SELF command should be issued only after the last read data has been appeared on DQ.
To exit the Self-refresh mode, apply minimum t
(NOP) or the Deselect command (DESL) should be asserted within one t
within one t
the detail.
It is recommended to assert an Auto-refresh command just after the t
period.
The mode register of SDR I/F FCRAM provides a variety of operations. The register consists of 3 operation
fields; Burst Length, Burst Type, and CAS latency. Refer to “ MODE REGISTER TABLE.”
The mode register can be programmed by the Mode Register Set command (MRS) . Each field is set by the
address line. Once a mode register is programmed, the contents of the register will be held until re-programmed
by another MRS command (or part loses power) . MRS command should be issued only when DQ is in High-Z.
The condition of the mode register is undefined after the power-up stage. It is required to set each field after
initialization of SDR I/F FCRAM. Refer to “17. Power-Up Initialization”.
SDR I/F FCRAM internal condition after power-up will be undefined. It is required to follow the following Power
On Sequence to execute read or write operation.
In addition, it is recommended that DQM and CKE track V
Register Set command (MRS) can be set before 2 Auto-refresh commands (REF) . It is possible to excute 5
before 4.
1. Apply the power and start the clock. Attempt to maintain either NOP or DESL command at the input.
2. Maintain stable power, stable clock, and NOP condition for a minimum of 500 s.
3. Precharge all banks by Precharge (PRE) or Precharge All command (PALL) .
4. Assert minimum of 2 Auto-refresh commands (REF) .
5. Program the mode register by Mode Register Set command (MRS) .
1 ms prior to the self-refresh mode entry.
ms after the Self-refresh exit.
REFC
period after t
SI
. Refer to “16. Self-Refresh Entry and Exit Timing” in “ TIMING DIAGRAMS” for
SI
MB81ES171625/173225-15-X
after CKE brought high, and then the No operation command
DD
to insure that output is in High-Z state. The Mode
REFC
period to avoid the violation of refresh
REFC
period. CKE should be held High
Low (SELF) . Once
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