IXXBB1 Fujitsu Microelectronics, Inc., IXXBB1 Datasheet - Page 83

• Manufacturer Part Number: IXXBB1
• Description: 32-bit Proprietary Microcontroller Cmos Fr60 Mb91301 Series
• Manufacturer: Fujitsu Microelectronics, Inc.

11. DMAC (DMA Controller)
Hardware Configuration
Main Functions of the DMA Controller
The DMA controller is used to perform DMA (direct memory access) transfer on the FR family device.
Using DMA transfer under the control of the DMA controller improves system performance by enabling data to
be transferred at high speed independently of the CPU.
• Independent DMA channels
• 5-channel independent access control circuits
• 32-bit address register (Supports reloading : 2 per channel)
• 16-bit transfer count register (Supports reloading : 1 per channel)
• 4-bit block count register (1 per channel)
• External transfer request input pins : DREQ0, DREQ1 (ch0, ch1 only)
• External transfer request acknowledge output pins : DACK0, DACK1 (ch0, ch1 only)
• DMA completion output pins : DEOP0, DEOP1 (ch0, ch1 only)
• fly-by transfer (memory to I/O , I/O to memory) (ch0, ch1 only)
• Two-cycle transfer
• Supports independent data transfer for multiple channels (5 channels)
(1) Priority order (ch 0
(2) Order can be reversed for ch 0 and ch 1
(3) DMAC activation triggers
(4) Transfer modes
Input from dedicated external pin (edge detection/level detection, ch 0, ch 1 only)
Request from built-in peripheral (shared interrupt request, including external interrupts)
Software request (register write)
Demand transfer, burst transfer, step transfer, or block transfer
Data type : byte/half-word/word
Single-shot or reload operation selectable
Addressing mode: Full 32-bit address (increment/decrement/fixed)
(address increment can be in the range 255 to 255)
ch 1
ch 2
5 channels
ch 3
ch 4)
MB91301 Series
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