IXXBB1 Fujitsu Microelectronics, Inc., IXXBB1 Datasheet - Page 26

• Manufacturer Part Number: IXXBB1
• Description: 32-bit Proprietary Microcontroller Cmos Fr60 Mb91301 Series
• Manufacturer: Fujitsu Microelectronics, Inc.

26
MB91301 Series
R15 (General purpose register)
RETI instruction
Notes on the PS register
A/D converter
Watchdog timer
When any of the following instructions is executed, the SSP* or USP* value is not used as R15, resulting in an
incorrect value written to memory.
Please do not neither control register of the instruction cache nor the data access to RAM of the instruction
cache immediately before the instruction of RETI.
Since some instructions manipulate the PS register earlier, the following exceptions may cause the interrupt
handler to break or the PS flag to update its display setting when the debugger is being used. As the microcon-
troller is designed to carry out reprocessing correctly upon returning from such an EIT event, it performs oper-
ations before and after the EIT as specified in either case.
When the device is turned on or returns from a reset or stop, it takes time for the external capacitor to be charged,
requiring the A/D converter to wait for at least 10 ms.
The watchdog timer function of this model monitors that a program delays a reset within a certain period of time
and resets the CPU if the program fails to delay it, for example, because the program runs out of control. Once
the watchdog timer function is enabled, therefore, the watchdog timer continues to operate until a reset takes
place.
An exception, for example during stop, sleep and DMA transfer modes, is the automatic delaying of a reset under
a condition in which the CPU stops program execution.
Note, however, that a watchdog reset may not occur in the above state caused when the system runs out of
control. If this is the case, use the external INIT pin to cause a reset (INIT) .
The following operations may be performed when the instruction immediately followed by a DIVOU/DIVOS
instruction is (a) halted by a user interrupt or NMI, (b) single-stepped, or (c) breaks in response to a data
event or emulator menu:
The following operations are performed when the ORCCR/STILM/MOV Ri and PS instructions are executed
to enable interruptions when a user interrupt or NMI trigger event has occurred.
(1) D0 and D1 flags are updated earlier.
(2) The EIT handler (user interrupt/NMI or emulator) is executed.
(3) Upon returning from the EIT, the DIVOU/DIVOS instruction is executed and the D0 and D1 flags are
(1) The PS register is updated earlier.
(2) The EIT handler (user interrupt/NMI or emulator) is executed.
(3) Upon returning from the EIT, the above instructions are executed and the PS register is updated to the
* : R15 is a virtual register. When a program attempts to access R15, the SSP or USP is accessed depending
on the status of the “S” flag as an SP flag. When coding the above ten instructions using an assembler,
specify a general-purpose register other than R15.
same value as that in (1) above.
updated to the same values as those in (1) above.
AND
OR
EOR
XCHB
R15, @Ri
R15, @Ri
R15, @Ri
@Rj, R15
ANDH
ORH
EORH
R15, @Ri
R15, @Ri
R15, @Ri
ANDB
ORB
EORB
R15, @Ri
R15, @Ri
R15, @Ri