IXXBB1 Fujitsu Microelectronics, Inc., IXXBB1 Datasheet - Page 54

• Manufacturer Part Number: IXXBB1
• Description: 32-bit Proprietary Microcontroller Cmos Fr60 Mb91301 Series
• Manufacturer: Fujitsu Microelectronics, Inc.

54
MB91301 Series
Control Registers
Cache Size Register (ISIZE)
Instruction Cache Control Register (ICHCR)
The instruction cache (I-cache) control register (ICHCR) controls the operations of the instruction cache.
Writing a value to the ICHCR has no effect on the caching of any instruction fetched within three cycles that follow.
Address
00010000
00010200
00010400
00010600
00010800
00010FFF
00014000
00014200
00014400
00014600
00014800
00014FFF
00018000
00018200
00018400
00018600
00018800
00018FFF
0001C000
0001C200
0001C400
0001C600
0001C800
0001CFFF
TAG RAM
00010000
00010004
00010008
0001000C
00010010
00010014
Address : 00000307
Address : 000003E7
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
TAG1 TAG RAM (way1)
TAG2 TAG RAM (way2)
RAM on/off RAM bit
Cache off
<IRAM1>
<IRAM2>
RAM off
IRAM1
IRAM2
Mirror area
bit
bit
H
H
RAM
R/W
<IRAM1>
<IRAM2>
7
Cache off
7
<TAG1>
<TAG2>
Entry at address 00x
Mirror of 00x
Entry at address 00x
Mirror of 00x
RAM on
IRAM1
IRAM2
TAG1
TAG2
6
6
Cache 4 K
I/O
RAM off
GBLK
R/W
5
5
$RAM1 Cache RAM (way1) IRAM1 I-bus RAM (way1)
$RAM2 Cache RAM (way2) IRAM1 I-bus RAM (way2)
Cache 4 K
<$RAM1>
<$RAM2>
RAM on
ALFL
<TAG1>
<TAG2>
$RAM1
$RAM2
R/W
TAG1
TAG2
4
4
Cache RAM
00018000
00018004
00018008
0001800C
00018010
00018014
EOLK
R/W
Cache 2 K
3
3
<IRAM1>
<IRAM2>
RAM off
IRAM1
IRAM2
ELKR
H
H
H
H
H
H
R/W
2
2
Cache 2 K
<$RAM1>
<$RAM2>
RAM on
<TAG1>
<TAG1>
<TAG2>
<TAG2>
$RAM1
$RAM2
IRAM1
IRAM2
TAG1
TAG2
SIZE1
FLSH
R/W
R/W
1
1
Instruction at address 000 (SBV0)
Instruction at address 004 (SBV1)
Instruction at address 008 (SBV2)
Instruction at address 00C (SBV3)
Instruction at address 010 (SBV0)
Instruction at address 014 (SBV1)
Cache 1 K
SIZE0
ENAB
RAM off
R/W
R/W
<IRAM1>
<IRAM2>
IRAM1
IRAM2
0
0
- - - - - - 10
Initial value
0 - 000000
Initial value
<$RAM1>
<$RAM2>
RAM on
<TAG1>
<TAG1>
<TAG1>
<TAG1>
<TAG2>
<TAG2>
<TAG2>
<TAG2>
Cache
$RAM1
$RAM2
IRAM1
IRAM2
TAG1
TAG2
B
B