IXXBB1 Fujitsu Microelectronics, Inc., IXXBB1 Datasheet - Page 28

• Manufacturer Part Number: IXXBB1
• Description: 32-bit Proprietary Microcontroller Cmos Fr60 Mb91301 Series
• Manufacturer: Fujitsu Microelectronics, Inc.

28
MB91301 Series
Configuration batch file
Emulation memory
The example batch file below sets the mode vector and sets up the CS0 configuration register for the download
area. Use values appropriate to the hardware in the wait, timing, and other settings.
#---------------------------------------------------------
# Set MODR (0x7fd) =Enable In memory+16 bit External Bus
set mem/byte 0x7fd=0x5
#---------------------------------------------------------
# Set ASR0 (0x640) ; 0x0010_0000 - 0x002f_ffff
set mem/halfword 0x640=0x0010
#---------------------------------------------------------
# Set ACR0 (0x642)
#
#
MODR
#
#
#
#
#
#
set mem/harfword 0x642=0x5462
#---------------------------------------------------------
# Set AWR0 (0x660)
#
#
#
#
#
#
#
#
set mem/halfword 0x660=0x2058
#---------------------------------------------------------
If SRAM as the emulation memory is built on target board, SRAM for be accessed by RD, WR signal, and BYTE
control signal can not be used. (The external bus is initialized to the bus mode for accessing RD, WRn after reset.)
; ASZ [3:0]=0101:2 Mbytes
; DBW [1:0]=01:16 bit width, automatically set from
; BST [1:0]=00:1 burst (16 bit x 2)
; SREN=0:Disable BRQ
; PFEN=1:Enable Pre fetch buffer
; WREN=1:Enable Write operation
; LEND=0: Big endian
; TYPE [3:0]=0010:WEX: Disable RDY
; W15-12=0010:auto wait=2
; WR07, 06=01:RD, WR delay=1cycle
; W05, 04=01:WR->WR delay=1cycle (for WEX)
; W03 =1:MCLK->RD/WR delay=0.5cycle
;
; W02 =0:ADR->CS delay=0
; W01 =0:ADR->RD/WR setup 0cycle
; W00 =RD/WR->ADR hold 0cycle
:for async Memory