IXXBB1 Fujitsu Microelectronics, Inc., IXXBB1 Datasheet - Page 53

• Manufacturer Part Number: IXXBB1
• Description: 32-bit Proprietary Microcontroller Cmos Fr60 Mb91301 Series
• Manufacturer: Fujitsu Microelectronics, Inc.

[bit 31 to bit 9] Address tag
[bit 7 to bit4] SBV3 to SBV0 : Sub-block validation
[bit 3] TAGV : Tag validation bit
[bit 1] LRU (only in way 1)
[bit 0] ETLK : Entry lock
Instruction Cache Tags
The address tag stores the upper 23 bits of the memory address of the instruction cached in the corresponding
block.
For example, memory address IA of the instruction data stored in sub-block k in block i is obtained from the
following equation:
IA
The address tag is used to check for a match with the instruction address requested for access by the CPU.
The CPU and cache behave as follows depending on the result of the tag check:
• When the requested instruction data exists in the cache (hit), the cache transfers the data to the CPU within
• When the requested instruction data does not exist in the cache (miss), the CPU and cache obtain the data
When SBV
by the tag. Each sub-block usually holds two instructions (excluding immediate-value transfer instructions).
This bit indicates whether the address tag value is valid. When the bit contains "0", the corresponding block is
invalid regardless of the settings of the sub-block validation bits. (The bit is set to "0" when the cache is flushed.)
This bit exists only in the instruction cache tag in way 1. The bit indicates way 1 or 2 as the way containing the
last entry accessed in the selected set. When set to "1", the LRU bit indicates that the entry of the set in way 1
is the last entry accessed. When set to "0", it indicates that the one in way 2 is the last entry accessed.
This bit is used to lock all the entries in the block corresponding to the tag in the cache. When the ETLK bit is
set to "1", the entries are locked and are not updated when a cache miss occurs. Note, however, that invalid
sub-blocks are updated. If a cache miss occurs with both of ways 1 and 2 in the entry lock states, access to
external memory takes place after losing one cycle used for evaluating the cache miss.
the cycle.
loaded by external access at the same time.
address tag
Way 2
Way 1
n
31
31
contains "1", the corresponding sub-block holds the current instruction data at the address located
2
9
i
2
4
Address tag
Address tag
k
SBV3
SBV3
2
07
07
2
SBV2
SBV2
06
06
SBV1
SBV1
05
05
SBV0
SBV0
09
09
04
04
Vacancy
Vacancy
TAGV
TAGV
08
08
03
03
Vacancy
02
02
MB91301 Series
Vacancy
LRU
01
01
ETLK
ETLK
00
00
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