HMP351U6MMP8C Hynix Semiconductor, HMP351U6MMP8C Datasheet - Page 9
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HMP351U6MMP8C
Manufacturer Part Number
HMP351U6MMP8C
Description
240pin Ddr2 Sdram Unbuffered Dimms Based On 2gb M Version
Manufacturer
Hynix Semiconductor
Datasheet
1.HMP351U6MMP8C.pdf
(21 pages)
Rev. 0.1 / May 2008
INPUT DC LOGIC LEVEL
INPUT AC LOGIC LEVEL
AC INPUT TEST CONDITIONS
Notes :
1.
2.
3.
dc Input logic HIGH
dc Input logic LOW
AC Input logic High
AC Input logic Low
V
V
SLEW
REF
SWING(MAX)
Input waveform timing is referenced to the input signal crossing through the V
under test.
The input signal minimum slew rate is to be maintained over the range from V
and the range from V
AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and
VIH(ac) to VIL(ac) on the negative transitions.
Symbol
Parameter
Parameter
V
Falling Slew =
SWING(MAX)
Input reference voltage
Input signal maximum peak to peak swing
Input signal minimum slew rate
delta TF
V
V
V
V
Symbol
Symbol
IH
IL
IH
IL
REF
(AC)
(AC)
V
(DC)
(DC)
REF
to V
< Figure : AC Input Test Signal Waveform >
- V
delta TF
IL(ac)
V
IL(ac)
Condition
REF
max for falling edges as shown in the below figure.
Min
+ 0.250
-
max
DDR2 400, 533
V
REF
-0.30
Min
+ 0.125
V
1240pin DDR2 SDRAM Unbuffered DIMMs
REF
Max
- 0.250
-
delta TR
Rising Slew =
V
0.5 * V
REF
Value
Min
1.0
1.0
+ 0.200
-
DDR2 667, 800
DDQ
V
V
REF
DDQ
REF
Max
REF
- 0.125
V
+ 0.3
IH(ac)
level applied to the device
V
to V
REF
Units
V/ns
Max
V
V
V
V
V
V
V
delta TR
IH(ac)
min - V
V
V
- 0.200
-
DDQ
IH(ac)
IH(dc)
REF
IL(dc)
IL(ac)
SS
min for rising edges
REF
max
max
min
min
Unit
Unit
V
V
V
V
Notes
2, 3
1
1
Note
Note
9