HMP351U6MMP8C Hynix Semiconductor, HMP351U6MMP8C Datasheet - Page 10
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HMP351U6MMP8C
Manufacturer Part Number
HMP351U6MMP8C
Description
240pin Ddr2 Sdram Unbuffered Dimms Based On 2gb M Version
Manufacturer
Hynix Semiconductor
Datasheet
1.HMP351U6MMP8C.pdf
(21 pages)
Differential Input AC logic Level
1. V
2. V
Notes:
1. V
DIFFERENTIAL AC OUTPUT PARAMETERS
Note:
1. The typical value of V
2. The typical value of V
Rev. 0.1 / May 2008
LDQS, UDQS and UDQS.
(such as CK, DQS, LDQS or UDQS) level and V
(such as CK, DQS, LDQS or UDQS) and V
level. The minimum value is equal to V
The minimum value is equal to V
track variations in V
Symbol
V
V
V
Symbol
track variations in V
IN
ID
ID
ID
OX
IX
(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS,
(DC) specifies the input differential voltage |V
(AC) specifies the input differential voltage |V
(ac)
(ac)
(ac)
ac differential input voltage
ac differential cross point voltage
ac differential cross point voltage
DDQ
DDQ
OX
IX
V
V
(AC) is expected to be about 0.5 * V
(AC) is expected to be about 0.5 * V
. V
CP
TR
. V
Parameter
Parameter
OX
IX
(AC) indicates the voltage at whitch differential input signals must cross.
(AC) indicates the voltage at whitch differential output signals must cross.
IH
(AC) - V
IH
< Differential signal levels >
(DC) - V
CP
IL
is the complementary input signal (such as CK, DQS, LDQS or UDQS).
(AC).
CP
TR
TR
IL
-V
-V
is the complementary input (such as CK, DQS, LDQS or UDQS)
(DC).
1240pin DDR2 SDRAM Unbuffered DIMMs
V
V
CP
0.5 * V
CP
0.5 * V
DDQ
SSQ
V
| required for switching, where V
| required for switching, where V
ID
DDQ
DDQ
DDQ
Min.
DDQ
Min.
0.5
of the transmitting device and V
of the transmitting device and V
- 0.175
- 0.125
V
0.5 * V
0.5 * V
IX or
V
DDQ
Crossing point
DDQ
DDQ
Max.
Max.
V
OX
+ 0.6
+ 0.175
+ 0.125
TR
TR
is the true input signal
is the true input
OX
IX
(AC) is expected to
(AC) is expected to
Units
Units
V
V
V
Note
Note
1
1
2
10