HMP351U6MMP8C Hynix Semiconductor, HMP351U6MMP8C Datasheet - Page 18
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HMP351U6MMP8C
Manufacturer Part Number
HMP351U6MMP8C
Description
240pin Ddr2 Sdram Unbuffered Dimms Based On 2gb M Version
Manufacturer
Hynix Semiconductor
Datasheet
1.HMP351U6MMP8C.pdf
(21 pages)
Rev. 0.1 / May 2008
Notes :
1. For details and notes, please refer to the relevant HYNIX component datasheet (HY5PS1G[8,16]31CFP).
2. 0°C ≤ TCASE ≤ 85°C
3. 85°C < TCASE ≤ 95°C
CAS to CAS command delay
Write recovery time
Auto precharge write recovery + precharge time tDAL
Internal write to read command delay
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
Exit precharge power down to any non-read
command
Exit active power down to read command
Exit active power down to read command
(Slow exit, Lower power)
CKE minimum pulse width
(high and low pulse width)
ODT turn-on delay
ODT turn-on
ODT turn-on(Power-Down mode)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down mode)
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
Minimum time clocks remains ON after CKE
asynchronously drops LOW
Average periodic Refresh Interval
Parameter
tCCD
tWR
tWTR
tRTP
tXSNR
tXSRD
tXP
tXARD
tXARDS
tCKE
tAOND
tAON
tAONPD
tAOFD
tAOF
tAOFPD
tANPD
tAXPD
tOIT
tDelay
tREFI
tREFI
Symbol
1240pin DDR2 SDRAM Unbuffered DIMMs
tIS+tCK+tIH
tAC(min)+2
tRFC + 10
tAC(min)
tAC(min)
tAC(min)
WR+tRP
7 - AL
min
200
2.5
7.5
7.5
+2
15
2
2
3
2
3
8
0
-
-
2
DDR2-667
tAC(max)+1
tAC(max)+1
tAC(max)+
tAC(max)
2.5tCK+
2tCK+
max
+0.7
2.5
0.6
7.8
3.9
12
2
-
-
-
-
-
tAC(min)
tAC(min)
tAC(min)
tAC(min)
WR+tRP
tIS+tCK
tRFC +
8 - AL
min
+tIH
200
2.5
7.5
7.5
+2
+2
10
15
2
2
3
2
3
8
0
-
-
2
DDR2-800
tAC(max)+1
tAC(max)+1
tAC(max)
tAC(max)
2.5tCK+
2tCK+
max
+0.7
+0.6
2.5
7.8
3.9
12
2
-
-
-
-
-
- continued -
Unit Note
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
us
ns
2
3
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