DSPIC30F6012A Microchip Technology Inc., DSPIC30F6012A Datasheet - Page 95

• Manufacturer Part Number: DSPIC30F6012A
• Description: Dspic30f6011a/6012a/6013a/6014a High-performance Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

14.3
The SSx pin allows a Synchronous Slave mode. The
SPI must be configured in SPI Slave mode with SSx pin
control enabled (SSEN = 1). When the SSx pin is low,
transmission and reception are enabled and the SDOx
pin is driven. When SSx pin goes high, the SDOx pin is
no longer driven. Also, the SPI module is re-
synchronized, and all counters/control circuitry are
reset. Therefore, when the SSx pin is asserted low
again, transmission/reception will begin at the MSb
even if SSx had been deasserted in the middle of a
transmit/receive.
14.4
During Sleep mode, the SPI module is shutdown. If the
CPU enters Sleep mode while an SPI transaction is in
progress, then the transmission and reception is
aborted.
The transmitter and receiver will stop in Sleep mode.
However, register contents are not affected by entering
or exiting Sleep mode.
© 2006 Microchip Technology Inc.
Slave Select Synchronization
SPI Operation During CPU Sleep
Mode
dsPIC30F6011A/6012A/6013A/6014A
Preliminary
14.5
When the device enters Idle mode, all clock sources
remain functional. The SPISIDL bit (SPIxSTAT<13>)
selects if the SPI module will stop or continue on Idle. If
SPISIDL = 0, the module will continue to operate when
the CPU enters Idle mode. If SPISIDL = 1, the module
will stop when the CPU enters Idle mode.
SPI Operation During CPU Idle
Mode
DS70143C-page 93