DSPIC30F6012A Microchip Technology Inc., DSPIC30F6012A Datasheet - Page 133
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DSPIC30F6012A
Manufacturer Part Number
DSPIC30F6012A
Description
Dspic30f6011a/6012a/6013a/6014a High-performance Digital Signal Controllers
Manufacturer
Microchip Technology Inc.
Datasheet
1.DSPIC30F6012A.pdf
(238 pages)
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The 20-bit mode treats each 256-bit AC-Link frame as
sixteen, 16-bit time slots. In the 20-bit AC-Link mode,
the module operates as if COFSG<3:0> = 1111 and
WS<3:0> = 1111. The data alignment for 20-bit data
slots is ignored. For example, an entire AC-Link data
frame can be transmitted and received in a packed
fashion by setting all bits in the TSCON and RSCON
SFRs. Since the total available buffer length is 64 bits,
it would take 4 consecutive interrupts to transfer the
AC-Link frame. The application software must keep
track of the current AC-Link frame segment.
18.7
The DCI module is configured for I
a value of ‘01’ to the COFSM<1:0> control bits in the
DCICON1 SFR. When operating in the I
DCI module will generate frame synchronization sig-
nals with a 50% duty cycle. Each edge of the frame
synchronization signal marks the boundary of a new
data word transfer.
The user must also select the frame length and data
word size using the COFSG and WS control bits in the
DCICON2 SFR.
© 2006 Microchip Technology Inc.
I
2
S Mode Operation
dsPIC30F6011A/6012A/6013A/6014A
2
S mode by writing
2
S mode, the
Preliminary
18.7.1
The WS and COFSG control bits are set to produce the
period for one half of an I
frame length is the total number of CSCK cycles
required for a left or a right data word transfer.
The BLEN bits must be set for the desired buffer length.
Setting BLEN<1:0> = 01 will produce a CPU interrupt,
once per I
18.7.2
As per the I
by default, begin one CSCK cycle after a transition of
the WS signal. A MSb left justified option can be
selected using the DJST control bit in the DCICON1
SFR.
If DJST = 1, the I
tified. The MSb of the data word will be presented on
the CSDO pin during the same CSCK cycle as the ris-
ing or falling edge of the COFS signal. The CSDO pin
is tri-stated after the data word has been sent.
2
S frame.
I
LENGTH SELECTION
I
2
2
2
S specification, a data word transfer will,
S FRAME AND DATA WORD
S DATA JUSTIFICATION
2
S data transfers will be MSb left jus-
2
S data frame. That is, the
DS70143C-page 131