DSPIC30F6012A Microchip Technology Inc., DSPIC30F6012A Datasheet - Page 156

• Manufacturer Part Number: DSPIC30F6012A
• Description: Dspic30f6011a/6012a/6013a/6014a High-performance Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A
20.4.1
A power-on event will generate an internal POR pulse
when a V
at the POR circuit threshold voltage (V
nominally 1.85V. The device supply voltage character-
istics must meet specified starting voltage and rise rate
requirements. The POR pulse will reset a POR timer
and place the device in the Reset state. The POR also
selects the device clock source identified by the
oscillator configuration fuses.
FIGURE 20-3:
FIGURE 20-4:
DS70143C-page 154
PWRT Time-out
PWRT Time-out
OST Time-out
Internal Reset
OST Time-out
Internal Reset
DD
Internal POR
Internal POR
POR: POWER-ON RESET
rise is detected. The Reset pulse will occur
MCLR
MCLR
V
V
DD
DD
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO V
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V
POR
), which is
T
T
OST
OST
Preliminary
T
PWRT
T
PWRT
The POR circuit inserts a small delay, T
nominally 10
circuits are stable. Furthermore, a user selected power-
up time-out (T
is based on device Configuration bits and can be 0 ms
(no delay), 4 ms, 16 ms or 64 ms. The total delay is at
device power-up T
have expired, SYSRST will be negated on the next
leading edge of the Q1 clock, and the PC will jump to
the Reset vector.
The timing for the SYSRST signal is shown in
Figure 20-3 through Figure 20-5.
PWRT
s and ensures that the device bias
POR
) is applied. The T
© 2006 Microchip Technology Inc.
+ T
DD
PWRT
)
. When these delays
DD
): CASE 1
PWRT
POR
parameter
, which is