DSPIC30F4013 Microchip Technology Inc., DSPIC30F4013 Datasheet - Page 92

• Manufacturer Part Number: DSPIC30F4013
• Description: Dspic30f3014/4013 High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

dsPIC30F3014/4013
14.12.2
Master mode reception is enabled by programming the
Receive Enable bit, RCEN (I2CCON<3>). The I
module must be Idle before the RCEN bit is set, other-
wise the RCEN bit is disregarded. The Baud Rate Gen-
erator begins counting and on each rollover, the state
of the SCL pin ACK and data are shifted into the
I2CRSR on the rising edge of each clock.
14.12.3
In I
located in the I2CBRG register. When the BRG is
loaded with this value, the BRG counts down to ‘0’ and
stops until another reload has taken place. If clock
arbitration is taking place, for instance, the BRG is
reloaded when the SCL pin is sampled high.
As per the I
400 kHz. However, the user can specify any baud rate
up to 1 MHz. I2CBRG values of ‘0’ or ‘1’ are illegal.
EQUATION 14-1:
14.12.4
Clock arbitration occurs when the master de-asserts
the SCL pin (SCL allowed to float high) during any
receive, transmit, or Restart/Stop condition. When the
SCL pin is allowed to float high, the Baud Rate Gener-
ator (BRG) is suspended from counting until the SCL
pin is actually sampled high. When the SCL pin is sam-
pled high, the Baud Rate Generator is reloaded with
the contents of I2CBRG and begins counting. This
ensures that the SCL high time is always at least one
BRG rollover count in the event that the clock is held
low by an external device.
14.12.5
Multi-master operation support is achieved by bus arbi-
tration. When the master outputs address/data bits
onto the SDA pin, arbitration takes place when the
master outputs a ‘1’ on SDA by letting SDA float high
while another master asserts a ‘0’. When the SCL pin
floats high, data should be stable. If the expected data
on SDA is a ‘1’ and the data sampled on the SDA
pin = 0, then a bus collision has taken place. The
master sets the MI2CIF pulse and resetS the master
portion of the I
DS70138E-page 90
2
C Master mode, the reload value for the BRG is
I2CBRG =
I
BAUD RATE GENERATOR
CLOCK ARBITRATION
MULTI-MASTER COMMUNICATION,
BUS COLLISION AND BUS
ARBITRATION
2
2
C MASTER RECEPTION
C standard, FSCK may be 100 kHz or
2
C port to its Idle state.
(
F
F
SCK
SERIAL CLOCK RATE
CY
–
1,111,111
F
CY
)
– 1
2
C
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the TBF flag is
cleared, the SDA and SCL lines are de-asserted and a
value can now be written to I2CTRN. When the user
services the I
tine, if the I
can resume communication by asserting a Start
condition.
If a Start, Restart, Stop or Acknowledge condition was
in progress when the bus collision occurred, the condi-
tion is aborted, the SDA and SCL lines are de-asserted,
and the respective control bits in the I2CCON register
are cleared to ‘0’. When the user services the bus
collision Interrupt Service Routine, and if the I
free, the user can resume communication by asserting
a Start condition.
The master continues to monitor the SDA and SCL
pins, and if a Stop condition occurs, the MI2CIF bit is
set.
A write to the I2CTRN starts the transmission of data at
the first data bit, regardless of where the transmitter left
off when bus collision occurred.
In a multi-master environment, the interrupt generation
on the detection of Start and Stop conditions allows the
determination of when the bus is free. Control of the I
bus can be taken when the P bit is set in the I2CSTAT
register, or the bus is Idle and the S and P bits are
cleared.
14.13 I
14.13.1
When the device enters Sleep mode, all clock sources
to the module are shut down and stay at logic ‘0’. If
Sleep occurs in the middle of a transmission and the
state machine is partially into a transmission as the
clocks stop, then the transmission is aborted. Similarly,
if Sleep occurs in the middle of a reception, then the
reception is aborted.
14.13.2
For the I
stops or continues on Idle. If I2CSIDL = 0, the module
continues operation on assertion of the Idle mode. If
I2CSIDL = 1, the module stops on Idle.
2
Sleep and Idle Modes
2
C, the I2CSIDL bit determines if the module
2
C Module Operation During CPU
I
SLEEP MODE
I
MODE
C bus is free (i.e., the P bit is set), the user
2
2
C OPERATION DURING CPU
C OPERATION DURING CPU IDLE
2
C master event Interrupt Service Rou-
© 2007 Microchip Technology Inc.
2
C bus is
2
C