DSPIC30F4013 Microchip Technology Inc., DSPIC30F4013 Datasheet - Page 141
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DSPIC30F4013
Manufacturer Part Number
DSPIC30F4013
Description
Dspic30f3014/4013 High-performance, 16-bit Digital Signal Controllers
Manufacturer
Microchip Technology Inc.
Datasheet
1.DSPIC30F4013.pdf
(220 pages)
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20.2.3
Enabling the LP oscillator is controlled with two
elements:
1.
2.
The LP oscillator is on (even during Sleep mode) if
LPOSCEN = 1. The LP oscillator is the device clock if:
• COSC<2:0> = 00 (LP selected as main oscillator)
• LPOSCEN = 1
Keeping the LP oscillator on at all times allows for a fast
switch to the 32 kHz system clock for lower power
operation. Returning to the faster main oscillator still
requires a start-up time
20.2.4
The PLL multiplies the clock which is generated by the
primary oscillator. The PLL is selectable to have either
gains of x4, x8, and x16. Input and output frequency
ranges are summarized in Table 20-3.
TABLE 20-3:
The PLL features a lock output which is asserted when
the PLL enters a phase locked state. Should the loop
fall out of lock (e.g., due to noise), the lock signal is
rescinded. The state of this signal is reflected in the
read-only LOCK bit in the OSCCON register.
20.2.5
The FRC oscillator is a fast (7.37 MHz ±2% nominal)
internal RC oscillator. This oscillator is intended to pro-
vide reasonable device operating speeds without the
use of an external crystal, ceramic resonator, or RC
network. The FRC oscillator can be used with the PLL
to obtain higher clock frequencies.
The dsPIC30F operates from the FRC oscillator when-
ever the current oscillator selection control bits in the
OSCCON register (OSCCON<14:12>) are set to ‘001’.
The
(OSCTUN<3:0>) allows the user to tune the internal
fast RC oscillator (nominal 7.37 MHz). The user can
tune the FRC oscillator within a range of +10.5% (840
kHz) and -12% (960 kHz) in steps of 1.50% around the
factory-calibrated setting, see Table 20-4.
If OSCCON<14:12> are set to ‘111’ and FPR<4:0> are
set to ‘00101’, ‘00110’ or ‘00111’, then a PLL
multiplier of 4, 8 or 16 (respectively) is applied.
© 2007 Microchip Technology Inc.
and
4 MHz-7.5 MHz
4 MHz-10 MHz
4 MHz-10 MHz
The current oscillator group bits COSC<2:0>.
The LPOSCEN bit (OSCCON register).
four-bit
F
IN
LP OSCILLATOR CONTROL
PHASE LOCKED LOOP (PLL)
FAST RC OSCILLATOR (FRC)
field
PLL FREQUENCY RANGE
Multiplier
PLL
x16
specified
x4
x8
64 MHz-120 MHz
16 MHz-40 MHz
32 MHz-80 MHz
by
F
OUT
TUN<3:0>
TABLE 20-4:
20.2.6
The LPRC oscillator is a component of the Watchdog
Timer (WDT) and oscillates at a nominal frequency of
512 kHz. The LPRC oscillator is the clock source for
the Power-up Timer (PWRT) circuit, WDT and clock
monitor circuits. It may also be used to provide a low-
frequency clock source option for applications where
power consumption is critical and timing accuracy is
not required.
The LPRC oscillator is always enabled at a Power-on
Reset because it is the clock source for the PWRT.
After the PWRT expires, the LPRC oscillator remains
on if one of the following is TRUE:
• The Fail-Safe Clock Monitor is enabled
• The WDT is enabled
• The LPRC oscillator is selected as the system
If one of the above conditions is not true, the LPRC
shuts off after the PWRT expires.
Note:
clock via the COSC<2:0> control bits in the
OSCCON register
TUN<3:0>
dsPIC30F3014/4013
Note 1: OSC2 pin function is determined by the
0111
0110
0101
0100
0011
0010
0001
0000
1111
1110
1101
1100
1011
1010
1001
1000
Bits
2: OSC1 pin cannot be used as an I/O pin
When a 16x PLL is used, the FRC
frequency must not be tuned to a
frequency greater than 7.5 MHz.
LOW-POWER RC OSCILLATOR
(LPRC)
Primary
(FPR<4:0>).
even if the secondary oscillator or an
internal clock source is selected at all
times.
Center Frequency (oscillator is
running at calibrated frequency)
FRC TUNING
Oscillator
FRC Frequency
+ 10.5%
+ 9.0%
+ 7.5%
+ 6.0%
+ 4.5%
+ 3.0%
+ 1.5%
- 1.5%
- 3.0%
- 4.5%
- 6.0%
- 7.5%
- 9.0%
- 10.5%
- 12.0%
DS70138E-page 139
mode
selection