DSPIC30F4013 Microchip Technology Inc., DSPIC30F4013 Datasheet - Page 120

• Manufacturer Part Number: DSPIC30F4013
• Description: Dspic30f3014/4013 High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

dsPIC30F3014/4013
18.3.6
When the DCI module is operating as a Frame Sync
slave (COFSD = 1), data transfers are controlled by the
Codec device attached to the DCI module. The
COFSM control bits control how the DCI module
responds to incoming COFS signals.
In the Multichannel mode, a new data frame transfer
begins one CSCK cycle after the COFS pin is sampled
high (see Figure 18-2). The pulse on the COFS pin
resets the Frame Sync generator logic.
FIGURE 18-2:
FIGURE 18-3:
FIGURE 18-4:
DS70138E-page 118
Note:
SLAVE FRAME SYNC OPERATION
CSDO or CSDI
CSDI or CSDO
CSDI/CSDO
A 5-bit transfer is shown here for illustration purposes. The I
will be system dependent.
BIT_CLK
CSCK
COFS
SYNC
CSCK
FRAME SYNC TIMING, MULTICHANNEL MODE
FRAME SYNC TIMING, AC-LINK START-OF-FRAME
I
2
S INTERFACE FRAME SYNC TIMING
WS
MSB
bit 2
S12
MSB
bit 1
S12
S12
LSb
MSb
Tag
bit 14
In the I
CSCK cycle after a low-to-high or a high-to-low transi-
tion is sampled on the COFS pin. A rising or falling
edge on the COFS pin resets the Frame Sync
generator logic.
In the AC-Link mode, the tag slot and subsequent data
slots for the next frame is transferred one CSCK cycle
after the COFS pin is sampled high.
The COFSG and WS bits must be configured to
provide the proper frame length when the module is
operating in the Slave mode. Once a valid Frame Sync
pulse has been sampled by the module on the COFS
pin, an entire data frame transfer takes place. The
module will not respond to further Frame Sync pulses
until the data frame transfer has completed.
Tag
LSB MSB
bit 13
Tag
2
2
S protocol does not specify word length – this
S mode, a new data word is transferred one
LSB
© 2007 Microchip Technology Inc.
LSB