DSPIC30F4013 Microchip Technology Inc., DSPIC30F4013 Datasheet - Page 150

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DSPIC30F4013

Manufacturer Part Number
DSPIC30F4013
Description
Dspic30f3014/4013 High-performance, 16-bit Digital Signal Controllers
Manufacturer
Microchip Technology Inc.
Datasheet

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dsPIC30F3014/4013
Table 20-5 shows the Reset conditions for the RCON
register. Since the control bits within the RCON register
are R/W, the information in the table means that all the
bits are negated prior to the action specified in the
condition column.
TABLE 20-5:
Table 20-6 shows a second example of the bit
conditions for the RCON register. In this case, it is not
assumed the user has set/cleared specific bits prior to
action specified in the condition column.
TABLE 20-6:
DS70138E-page 148
Power-on Reset
Brown-out Reset
MCLR Reset during normal
operation
Software Reset during
normal operation
MCLR Reset during Sleep
MCLR Reset during Idle
WDT Time-out Reset
WDT Wake-up
Interrupt Wake-up from Sleep PC + 2
Clock Failure Trap
Trap Reset
Illegal Operation Trap
Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’
Note 1:
Power-on Reset
Brown-out Reset
MCLR Reset during normal
operation
Software Reset during
normal operation
MCLR Reset during Sleep
MCLR Reset during Idle
WDT Time-out Reset
WDT Wake-up
Interrupt Wake-up from Sleep PC + 2
Clock Failure Trap
Trap Reset
Illegal Operation Reset
Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’
Note 1:
Condition
Condition
When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector.
When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector.
INITIALIZATION CONDITION FOR RCON REGISTER: CASE 1
INITIALIZATION CONDITION FOR RCON REGISTER: CASE 2
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000004
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000004
0x000000
0x000000
Program
Program
Counter
Counter
PC + 2
PC + 2
(1)
(1)
TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR
TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR
0
0
0
0
0
0
0
0
0
0
1
0
0
u
u
u
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u
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u
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u
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1
1
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u
u
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1
0
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0
0
© 2007 Microchip Technology Inc.
0
u
0
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0
1
0
u
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u
u
u
0
0
0
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1
0
0
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1
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u
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u
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u
u
u
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u
1
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1
1
0
0
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0
0
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0
0
0
0

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