DSPIC30F4013 Microchip Technology Inc., DSPIC30F4013 Datasheet - Page 129

• Manufacturer Part Number: DSPIC30F4013
• Description: Dspic30f3014/4013 High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

19.4
The conversion trigger terminates acquisition and
starts the requested conversions.
The SSRC<2:0> bits select the source of the conver-
sion trigger. The SSRC bits provide for up to 4 alternate
sources of conversion trigger.
When SSRC<2:0> = 000, the conversion trigger is
under software control. Clearing the SAMP bit causes
the conversion trigger.
When SSRC<2:0> = 111 (Auto-Convert mode), the
conversion trigger is under A/D clock control. The
SAMC bits select the number of A/D clocks between
the start of acquisition and the start of conversion. This
provides the fastest conversion rates on multiple
channels. SAMC must always be at least 1 clock cycle.
Other trigger sources can come from timer modules or
external interrupts.
19.5
Clearing the ADON bit during a conversion aborts the
current conversion and stops the sampling sequencing
until the next sampling trigger. The ADCBUF is not
updated with the partially completed A/D conversion
sample. That is, the ADCBUF will continue to contain
the value of the last completed conversion (or the last
value written to the ADCBUF register).
If clearing of the ADON bit coincides with an auto-start,
the clearing has a higher priority and a new conversion
does not start.
19.6
The ADC conversion requires 14 T
the ADC conversion clock is software selected, using a
six-bit counter. There are 64 possible options for T
EQUATION 19-1:
© 2007 Microchip Technology Inc.
Programming the Start of
Conversion Trigger
Aborting a Conversion
Selecting the ADC Conversion
Clock
T
AD
= T
CY
* (0.5*(ADCS<5:0> + 1))
CLOCK
ADC CONVERSION
AD
. The source of
AD
.
The internal RC oscillator is selected by setting the
ADRC bit.
For correct ADC conversions, the ADC conversion
clock (T
time of 334 nsec (for V
Specifications section for minimum T
operating conditions.
Example 19-1 shows a sample calculation for the
ADCS<5:0> bits, assuming a device operating speed
of 30 MIPS.
EXAMPLE 19-1:
Since,
Sampling Time = Acquisition Time + Conversion Time
Therefore,
Sampling Rate =
If SSRC<2:0> = ‘111’ and SAMC<4:0> = ‘00001’
dsPIC30F3014/4013
Therefore,
Set ADCS<5:0> = 9
AD
ADCS<5:0> = 2
Minimum T
) must be selected to ensure a minimum T
Actual T
= ~100 kHz
= 1 T
= 15 x 165 nsec
AD
T
(15 x 165 nsec)
AD
CY
AD
= 2 •
= 8.33
=
=
= 165 nsec
ADC CONVERSION
CLOCK CALCULATION
DD
= 154 nsec
= 33.33 nsec (30 MIPS)
+ 14 T
T
33.33 nsec
1
= 5V). Refer to the Electrical
T
T
CY
2
AD
33.33 nsec
CY
154 nsec
2
AD
(ADCS<5:0> + 1)
– 1
DS70138E-page 127
(19 + 1)
AD
– 1
under other
AD