DSPIC30F4012 Microchip Technology Inc., DSPIC30F4012 Datasheet - Page 90

• Manufacturer Part Number: DSPIC30F4012
• Description: Dspic30f4011/4012 Enhanced Flash 16-bit Digital Signal Controller
• Manufacturer: Microchip Technology Inc.

dsPIC30F4011/4012
14.7
Since the QEI module can function as a quadrature
encoder interface, or as a 16-bit timer, the following
section describes operation of the module in both
modes.
14.7.1
When the CPU is placed in the Idle mode, the QEI mod-
ule will operate if the QEISIDL bit (QEICON<13>) = 0.
This bit defaults to a logic ‘0’ upon executing POR and
BOR. For halting the QEI module during the CPU Idle
mode, QEISIDL should be set to ‘1’.
14.7.2
When the CPU is placed in the Idle mode and the QEI
module is configured in the 16-bit Timer mode, the
16-bit
(QEICON<13>) = 0. This bit defaults to a logic ‘0’ upon
executing POR and BOR. For halting the timer module
during the CPU Idle mode, QEISIDL should be set
to ‘1’.
If the QEISIDL bit is cleared, the timer will function
normally as if the CPU Idle mode had not been
entered.
DS70135E-page 88
timer
QEI Module Operation During CPU
Idle Mode
QEI OPERATION DURING CPU IDLE
MODE
TIMER OPERATION DURING CPU
IDLE MODE
will
operate
if
the
QEISIDL
bit
14.8
The quadrature encoder interface has the ability to
generate an interrupt on occurrence of the following
events:
• Interrupt on 16-bit up/down position counter
• Detection of qualified index pulse or if CNTERR
• Timer period match event (overflow/underflow)
• Gate accumulation event
The QEI Interrupt Flag bit, QEIIF, is asserted upon
occurrence of any of the above events. The QEIIF bit
must be cleared in software. QEIIF is located in the
IFS2 register.
Enabling an interrupt is accomplished via the respec-
tive Enable bit, QEIIE. The QEIIE bit is located in the
IEC2 register.
rollover/underflow
bit is set
Quadrature Encoder Interface
Interrupts
© 2007 Microchip Technology Inc.