DSPIC30F4012 Microchip Technology Inc., DSPIC30F4012 Datasheet - Page 121

• Manufacturer Part Number: DSPIC30F4012
• Description: Dspic30f4011/4012 Enhanced Flash 16-bit Digital Signal Controller
• Manufacturer: Microchip Technology Inc.

18.5.2
The FERR bit (UxSTA<2>) is set if a ‘0’ is detected
instead of a Stop bit. If two Stop bits are selected, both
Stop bits must be ‘1’, otherwise FERR will be set. The
read-only FERR bit is buffered along with the received
data; it is cleared on any Reset.
18.5.3
The PERR bit (UxSTA<3>) is set if the parity of the
received word is incorrect. This error bit is applicable
only if a Parity mode (odd or even) is selected. The
read-only PERR bit is buffered along with the received
data bytes; it is cleared on any Reset.
18.5.4
When the receiver is active (i.e., between the initial
detection of the Start bit and the completion of the Stop
bit), the RIDLE bit (UxSTA<4>) is ‘0’. Between the
completion of the Stop bit and detection of the next
Start bit, the RIDLE bit is ‘1’, indicating that the UART
is Idle.
18.5.5
The receiver will count and expect a certain number
of bit times based on the values programmed in
the
(UxMODE<0>) bits.
If the Break is longer than 13 bit times, the reception is
considered complete after the number of bit times
specified by PDSEL and STSEL. The URXDA bit is
set, FERR is set, zeros are loaded into the receive
FIFO, interrupts are generated, if appropriate and the
RIDLE bit is set.
When the module receives a long Break signal and the
receiver has detected the Start bit, the data bits and
the invalid Stop bit (which sets the FERR), the receiver
must wait for a valid Stop bit before looking for the next
Start bit. It cannot assume that the Break condition on
the line is the next Start bit.
Break is regarded as a character containing all ‘0’s,
with the FERR bit set. The Break character is loaded
into the buffer. No further reception can occur until a
Stop bit is received. Note that RIDLE goes high when
the Stop bit has not been received yet.
© 2007 Microchip Technology Inc.
PDSEL<1:0> (UxMODE<2:1>) and STSEL
FRAMING ERROR (FERR)
PARITY ERROR (PERR)
IDLE STATUS
RECEIVE BREAK
18.6
Setting the ADDEN bit (UxSTA<5>) enables this
special mode in which a 9th bit (URX8) value of ‘1’
identifies the received word as an address, rather than
data. This mode is only applicable for 9-bit data
communication. The URXISELx control bit does not
have any impact on interrupt generation in this mode,
since an interrupt (if enabled) will be generated every
time the received word has the 9th bit set.
18.7
Setting the LPBACK bit enables this special mode in
which the UxTX pin is internally connected to the UxRX
pin. When configured for the Loopback mode, the
UxRX pin is disconnected from the internal UART
receive logic. However, the UxTX pin still functions as
in a normal operation.
To select this mode:
a)
b)
c)
18.8
The UART has a 16-bit Baud Rate Generator to allow
maximum flexibility in baud rate generation. The Baud
Rate Generator register (UxBRG) is readable and
writable. The baud rate is computed as follows:
BRG = 16-bit value held in UxBRG register
F
The baud rate is given by Equation 18-1.
EQUATION 18-1:
Therefore, maximum baud rate possible is:
F
and the minimum baud rate possible is:
F
With a full, 16-bit Baud Rate Generator, at 30 MIPS
operation, the minimum baud rate achievable is
28.5 bps.
CY
CY
CY
dsPIC30F4011/4012
/16 (if BRG = 0),
/(16 * 65536).
Configure UART for desired mode of operation.
Set LPBACK = 1 to enable Loopback mode.
Enable transmission as defined in Section 18.3
“Transmitting Data”.
= Instruction Clock Rate (1/T
(0 through 65535)
Address Detect Mode
Loopback Mode
Baud Rate Generator
Baud Rate = F
BAUD RATE
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/(16 * (BRG + 1))
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DS70135E-page 119
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