DSPIC30F4012 Microchip Technology Inc., DSPIC30F4012 Datasheet - Page 157

• Manufacturer Part Number: DSPIC30F4012
• Description: Dspic30f4011/4012 Enhanced Flash 16-bit Digital Signal Controller
• Manufacturer: Microchip Technology Inc.

21.4
21.4.1
The primary function of the Watchdog Timer (WDT) is
to reset the processor in the event of a software
malfunction. The WDT is a free-running timer that runs
off an on-chip RC oscillator, requiring no external
component. Therefore, the WDT timer continues to
operate even if the main processor clock (e.g., the
crystal oscillator) fails.
21.4.2
The Watchdog Timer can be “Enabled” or “Disabled”
only through a Configuration bit (FWDTEN) in the
Configuration register, FWDT.
Setting FWDTEN = 1 enables the Watchdog Timer.
The enabling is done when programming the device.
By default, after chip erase, FWDTEN bit = 1. Any
device
dsPIC30F devices allows programming of this and
other Configuration bits.
If enabled, the WDT increments until it overflows or
“times out”. A WDT time-out forces a device Reset
(except during Sleep). To prevent a WDT time-out, the
user must clear the Watchdog Timer using a CLRWDT
instruction.
If a WDT times out during Sleep, the device wakes-up.
The WDTO bit in the RCON register is cleared to
indicate a wake-up resulting from a WDT time-out.
Setting FWDTEN = 0 allows user software to enable/
disable the Watchdog Timer via the SWDTEN
(RCON<5>) control bit.
21.5
There are two power-saving states that can be entered
through the execution of a special instruction, PWRSAV.
These are: Sleep and Idle.
The format of the PWRSAV instruction is as follows:
PWRSAV <parameter>, where ‘parameter’ defines
Idle or Sleep mode.
© 2007 Microchip Technology Inc.
Power-Saving Modes
programmer
Watchdog Timer (WDT)
WATCHDOG TIMER OPERATION
ENABLING AND DISABLING
THE WDT
capable
of
programming
21.5.1
In Sleep mode, the clock to the CPU and peripherals is
shut down. If an on-chip oscillator is being used, it is
shut down.
The Fail-Safe Clock Monitor is not functional during
Sleep, since there is no clock to monitor. However, the
LPRC clock remains active if WDT is operational during
Sleep.
The Brown-out Reset protection circuit and the Low-
Voltage Detect (LVD) circuit, if enabled, remain
functional during Sleep.
The processor wakes up from Sleep if at least one of
the following conditions has occurred:
• any interrupt that is individually enabled and
• any Reset (POR, BOR and MCLR)
• WDT time-out
On waking up from Sleep mode, the processor restarts
the same clock that was active prior to entry into Sleep
mode. When clock switching is enabled, bits
COSC<1:0> determine the oscillator source to be
used on wake-up. If clock switch is disabled, then
there is only one system clock.
If the clock source is an oscillator, the clock to the
device is held off until OST times out (indicating a
stable oscillator). If PLL is used, the system clock is
held off until LOCK = 1 (indicating that the PLL is
stable). In either case, T
are applied.
If EC, FRC, LPRC or ERC oscillators are used, then a
delay of T
delay possible on wake-up from Sleep.
Moreover, if the LP oscillator was active during Sleep,
and LP is the oscillator used on wake-up, then the start-
up delay is equal to T
not applied. In order to have the smallest possible start-
up delay when waking up from Sleep, one of these
faster wake-up options should be selected before
entering Sleep.
meets the required priority level
Note:
dsPIC30F4011/4012
POR
SLEEP MODE
If a POR or BOR occurred, the selection of
the oscillator is based on the FOS<1:0>
and FPR<3:0> Configuration bits.
(~10 μs) is applied. This is the smallest
POR
POR
. PWRT and OST delays are
, T
LOCK
DS70135E-page 155
and T
PWRT
delays