DSPIC30F4012 Microchip Technology Inc., DSPIC30F4012 Datasheet - Page 105

• Manufacturer Part Number: DSPIC30F4012
• Description: Dspic30f4011/4012 Enhanced Flash 16-bit Digital Signal Controller
• Manufacturer: Microchip Technology Inc.

16.0
The Serial Peripheral Interface (SPI) module is a
synchronous serial interface. It is useful for communi-
cating with other peripheral devices, such as
EEPROMs, shift registers, display drivers and A/D
converters, or other microcontrollers. It is compatible
with Motorola’s SPI and SIOP interfaces.
16.1
The SPI module consists of a 16-bit shift register,
SPI1SR, used for shifting data in and out, and a buffer
register, SPI1BUF. A control register, SPI1CON,
configures the module. Additionally, a status register,
SPI1STAT, indicates various status conditions.
The serial interface consists of 4 pins: SDI1 (Serial Data
Input), SDO1 (Serial Data Output), SCK1 (Shift Clock
Input or Output), and SS1 (active-low Slave Select).
In Master mode operation, SCK1 is a clock output, but
in Slave mode, it is a clock input.
A series of eight (8) or sixteen (16) clock pulses shift
out bits from the SPI1SR to SDO1 pin, and simulta-
neously, shifts in data from SDI1 pin. An interrupt is
generated when the transfer is complete and the
corresponding interrupt flag bit (SPI1IF) is set. This
interrupt can be disabled through an interrupt enable
bit (SPI1IE).
The receive operation is double-buffered. When a
complete byte is received, it is transferred from
SPI1SR to SPI1BUF.
If the receive buffer is full when new data is being
transferred from SPI1SR to SPI1BUF, the module will
set the SPIROV bit, indicating an overflow condition.
The transfer of the data from SPI1SR to SPI1BUF will
not be completed and the new data will be lost. The
module will not respond to SCL transitions while
SPIROV is ‘1’, effectively disabling the module until
SPI1BUF is read by user software.
Transmit writes are also double-buffered. The user
writes to SPI1BUF. When the master or slave transfer
is completed, the contents of the shift register
(SPI1SR) is moved to the receive buffer. If any trans-
mit data has been written to the buffer register, the
contents of the transmit buffer are moved to SPI1SR.
The received data is thus placed in SPI1BUF and the
transmit data in SPI1SR is ready for the next transfer.
© 2007 Microchip Technology Inc.
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the dsPIC30F Family Reference
Manual (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
Note:
SPI MODULE
Operating Function Description
Both the transmit buffer (SPI1TXB) and
the receive buffer (SPI1RXB) are mapped
to the same register address, SPI1BUF.
In Master mode, the clock is generated by prescaling
the system clock. Data is transmitted as soon as a
value is written to SPI1BUF. The interrupt is generated
at the middle of the transfer of the last bit.
In Slave mode, data is transmitted and received as
external clock pulses appear on SCK1. Again, the
interrupt is generated when the last bit is latched. If
SS1 control is enabled, then transmission and recep-
tion are enabled only when SS1 = low. The SDO1
output will be disabled in SS1 mode with SS1 high.
The clock provided to the module is (F
clock is then prescaled by the primary (PPRE<1:0>)
and secondary (SPRE<2:0>) prescale factors. The
CKE bit determines whether transmit occurs on transi-
tion from active clock state to Idle clock state, or vice
versa. The CKP bit selects the Idle state (high or low)
for the clock.
16.1.1
A control bit, MODE16 (SPI1CON<10>), allows the
module to communicate in either 16-bit or 8-bit mode.
16-bit operation is identical to 8-bit operation, except
that the number of bits transmitted is 16 instead of 8.
The user software must disable the module prior to
changing the MODE16 bit. The SPI module is reset
when the MODE16 bit is changed by the user.
A basic difference between 8-bit and 16-bit operation is
that the data is transmitted out of bit 7 of the SPI1SR
for 8-bit operation, and data is transmitted out of bit 15
of the SPI1SR for 16-bit operation. In both modes, data
is shifted into bit 0 of the SPI1SR.
16.1.2
A control bit, DISSDO, is provided to the SPI1CON
register to allow the SDO1 output to be disabled. This
will allow the SPI module to be connected in an input
only configuration. SDO1 can also be used for general
purpose I/O.
16.2
The module supports a basic framed SPI protocol in
Master or Slave mode. The control bit, FRMEN,
enables framed SPI support and causes the SS1 pin to
perform the frame synchronization pulse (FSYNC)
function. The control bit, SPIFSD, determines whether
the SS1 pin is an input or an output (i.e., whether the
module receives or generates the frame synchroniza-
tion pulse). The frame pulse is an active-high pulse for
a single SPI clock cycle. When frame synchronization
is enabled, the data transmission starts only on the
subsequent transmit edge of the SPI clock.
dsPIC30F4011/4012
Framed SPI Support
WORD AND BYTE
COMMUNICATION
SDO1 DISABLE
DS70135E-page 103
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