EVX10AS008BGL ETC-unknow, EVX10AS008BGL Datasheet - Page 4

• Manufacturer Part Number: EVX10AS008BGL
• Description: Adc Single 2.2gsps 10-bit Lvds 152-pin Cbga
• Manufacturer: ETC-unknow

2. Functional Description
3. Specifications
3.1
Table 3-1.
Note:
4
Parameter
Positive supply voltage
Digital positive supply voltage
Negative supply voltage
Analog input voltages (to ground)
Maximum difference between V
Clock input voltage
Clock input common mode voltage
Maximum difference between V
Static input voltage
Digital input voltage
Junction temperature
Absolute Maximum Ratings
Absolute maximum ratings are limiting values (referenced to GND = 0V), to be applied individually, while other parameters are
within specified operating conditions. Long exposure to maximum rating may affect device reliability.
All integrated circuits have to be handled with appropriate care to avoid damages due to ESD. Damage caused by inappropriate
handling or storage could range from performance degradation to complete failure. D
EV10AS008B.
0811A–BDC–12/08
Absolute Maximum Ratings
The EV10AS008B is a 10-bit 2.2 Gsps ADC. The device includes a front-end Track and Hold stage
(T/H), followed by an analog encoding stage (Analog Quantizer) which outputs analog residues resulting
from analog quantization. Successive banks of latches regenerate the analog residues into logical levels
before entering an error correction circuitry and a resynchronization stage followed by LVDS compatible
differential output buffers.
The EV10AS008B works in fully differential mode from analog inputs up to digital outputs. A differential
data ready output (DR/DRB) is available for optimum data valid time window. Asynchronous data ready
Reset ensures that the first digitized data is registered on rising edge of data ready output.
The Control pin B/GB (A11 of CBGA package) is provided to select either a binary or Gray data output
format. The gain control pin GA (R9 of CBGA package) is provided to adjust the ADC gain transfer func-
tion. A Sampling Delay Adjust function (SDA) is provided to fine tune the ADC aperture delay, for
applications requesting the interleaving of multiple ADCs for example SDA is enabled if SDAEN is
active. A pattern generator is integrated on chip for debug or acquisition set-up. This function is enabled
through the PGEB pin (A9 of CBGA package). An out-of-range bit (OR, ORB) indicates when the input
overrides the ADC full-scale range. A die junction temperature monitoring function is available (A10 of
CBGA package).
The EV10AS008B uses only vertical isolated NPN transistors together with oxide isolated polysilicon
resistors, which allows enhanced radiation tolerance (over 100 kRad (Si) expected total dose). The
EV10AS008B provides ascending compatibility with the AT84AS008.
IN
CLK
and V
and V
INB
CLKB
(V
V
V
CLK
V
CLK
V
CLK
Symbol
IN
V
IN
+ V
V
PLUSD
V
or V
or V
V
V
T
- V
- V
CC
EE
D
D
J
CLKB
INB
CLKB
INB
CLKB
)/2
SDAEN, DRRB,
B/GB, PGEB
Comments
GA, SDA
VEE
in AT84AS008 becomes DGND in
GND to –2.7
GND to 3.8
–1.5 to 1.5
–1.5 to 1.5
–0.7 to 0.6
–1.5 to 1.5
–0.5 to 3.8
GND to 3
–1 to 1
–1 to 1
e2v semiconductors SAS 2008
Value
135
EV10AS008B
Unit
°C
V
V
V
V
V
V
V
V
V
V