EVX10AS008BGL ETC-unknow, EVX10AS008BGL Datasheet - Page 33

• Manufacturer Part Number: EVX10AS008BGL
• Description: Adc Single 2.2gsps 10-bit Lvds 152-pin Cbga
• Manufacturer: ETC-unknow

8. EV10AS008B Application Information
8.1
8.1.1
8.1.2
8.1.3
8.1.4
e2v semiconductors SAS 2008
Timing Information
Timing Value for EV10AS008B
Propagation Time Considerations
TOD
Principle of Operation
–
TDR Variation over Temperature
Timing values are defined in
account package transmission line, bond wire, pad and ESD protections capacitance, and specified ter-
mination loads.
Evaluation board propagation delays in 50Ω controlled impedance traces are not taken into account.
Apply proper derating values corresponding to termination topology.
TOD and TDR timing values are given from package pin to pin and do not include the additional propa-
gation times between device pins and input/output termination loads. For the evaluation board, the
propagation time delay is 6.1 ps/mm (155 ps/inch) corresponding to 3.4 dielectric constant (at 10GHz) of
the RO4003 used for the board.
If a different dielectric layer is used (for instance Teflon), please use appropriate propagation time val-
ues. TD1 and TD2 do not depend on propagation times because they are differential data (
of Terms” on page 31.
TD1 and TD2 are also the most straightforward data to measure, because it is differential: TD can be
measured directly onto termination loads, with matched oscilloscope probes.
Values for TOD and TDR track each other over temperature (1 percent variation for TOD
degrees Celsius temperature variation). Therefore TOD
Moreover, the internal (on chip) skews between each data TODs and TDR effect can be considered as
negligible. Consequently, minimum values for TOD and TDR are never more than 100 ps apart. The
same is true for the TOD and TDR maximum values.
However, external TOD
(each digital data) and TDR: MCM board, bonding wires and output line length differences, and output
termination impedance mismatches.
The external (on board) skew effect has not been taken into account for the specification of the minimum
and maximum values for TOD
The analog input is sampled on the rising edge of external clock input (CLK,CLKB) after TA (aperture
delay). The digitized data is available after 4 clock periods latency (pipeline delay (TPD)), on clock rising
edge, after typical propagation delay TOD. The data ready differential output signal frequency (DR,
DRB) is half the external clock frequency, it switches at the same rate as the digital outputs. The data
ready output signal (DR, DRB) switches on external clock falling edge after a propagation delay TDR.
If TOD = TDR, the rising edge (True-False) of the differential data ready signal is placed in the middle of
the output data valid window. This gives maximum setup and hold times for external data acquisition.
A Master asynchronous reset input command DRRB (active high) is available for initializing the differen-
tial data ready output signal (DR,DRB). This feature is mandatory in certain applications using
).
–
TDR values may be dictated by total digital data skews between every TODs
Section
–
TDR.
3.3. Timing values are given at package inputs/outputs, taking into
–
TDR variation over temperature is negligible.
EV10AS008B
0811A–BDC–12/08
–
See “Definition
TDR per 100
33