EVX10AS008BGL ETC-unknow, EVX10AS008BGL Datasheet - Page 36

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EVX10AS008BGL

Manufacturer Part Number
EVX10AS008BGL
Description
Adc Single 2.2gsps 10-bit Lvds 152-pin Cbga
Manufacturer
ETC-unknow
Datasheet
8.3
8.3.1
8.3.2
36
Analog Inputs (VIN/VINB)
0811A–BDC–12/08
Static Issues: Differential vs. Single-ended (Full-scale Inputs)
Dynamic Issues: Input Impedance and VSWR
The ADC front-end Track and Hold differential preamplifier has been designed in order to be entered
either in differential mode or single-ended mode, up to maximum operating speed (2.2 Gsps), without
affecting dynamic performance (does not request a single to differential balun). In single-ended input
configuration, the in-phase full-scale input amplitude is 0.5V peak-to-peak, centered on 0V. (or
into 50Ω).
Figure 8-3.
The analog input full-scale range is 0.5V peak-to-peak (Vpp), or
termination resistor.
In differential mode input configuration, that means 0.25V on each input, or ±125 mV around zero volt.
The input common mode is ground.
Figure 8-4.
The EV10AS008B analog input features a 100Ω (±2%) differential input impedance (2
Each analog input (VIN,VINB) is terminated by on chip 50Ω single-ended (100Ω differential) resistors
(±2% matching). The ADC package Analog Inputs transmission lines feature a 50Ω controlled imped-
ance. Each single-ended die input pad capacitance (taking into account ESD protection) is 0.3 pF. This
leads to a global input VSWR (including ball, package and bounding) of less than 1.2 from DC up to 2.5
GHz.
500 mV
Full-scale
Analog Input
Typical Single-ended Analog Input Configuration (Full-scale)
Differential Inputs Voltage Span (Full-scale)
500 mV
Full-scale
Analog Input
+250
+125
mV
-250
mV
-125
VIN
VIN
2 dBm into the 50Ω (100Ω differential)
VINB = 0V
VINB
e2v semiconductors SAS 2008
EV10AS008B
0V
×
t
50Ω // 0.3 pF):
t
2 dBm

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