EVX10AS008BGL ETC-unknow, EVX10AS008BGL Datasheet - Page 31

• Manufacturer Part Number: EVX10AS008BGL
• Description: Adc Single 2.2gsps 10-bit Lvds 152-pin Cbga
• Manufacturer: ETC-unknow

7. Definition of Terms
Table 7-1.
e2v semiconductors SAS 2008
Term
Fs max
Fs min
BER
FPBW
SSBW
SINAD
SNR
THD
SFDR
ENOB
DNL
INL
TA
Definition of Terms
Maximum sampling
frequency
Minimum sampling
frequency
Bit error rate
Full power input bandwidth
Small signal input bandwidth
Signal-to-noise and
distortion ratio
Signal-to-noise ratio
Spurious-free dynamic range
Differential nonlinearity
Integral nonlinearity
Aperture delay
Total harmonic distortion
Effective number of bits
Description
Sampling frequency for which ENOB < 6 bits
Sampling frequency for which the ADC Gain has fallen by 0.5dB with respect
to the gain reference value. Performances are not guaranteed below this
frequency
Probability to exceed a specified error threshold for a sample at maximum
specified sampling rate. An error code is a code that differs by more than
LSB from the correct code
Analog input frequency at which the fundamental component in the digitally
reconstructed output waveform has fallen by 3 dB with respect to its low
frequency value (determined by FFT analysis) for input at full-scale –1 dB
(–1 dBFS)
Analog input frequency at which the fundamental component in the digitally
reconstructed output waveform has fallen by 3 dB with respect to its low
frequency value (determined by FFT analysis) for input at full-scale –10 dB
(–10 dBFS)
Ratio expressed in dB of the RMS signal amplitude, set to 1dB below full-
scale (–1 dBFS), to the RMS sum of all other spectral components, including
the harmonics except DC
Ratio expressed in dB of the RMS signal amplitude, set to 1 dB below full-
scale, to the RMS sum of all other spectral components excluding the nine
first harmonics
Ratio expressed in dB of the RMS sum of the first nine harmonic
components, to the RMS input signal amplitude, set at 1 dB below full-scale.
It may be reported in dB (i.e, related to converter –1 dB full-scale), or in dBc
(i.e, related to input signal level
Ratio expressed in dB of the RMS signal amplitude, set at 1dB below full-
scale, to the RMS value of the highest spectral component (peak spurious
spectral component). The peak spurious component may or may not be a
harmonic. It may be reported in dB (i.e., related to converter –1 dB full-scale),
or in dBc (i.e, related to input signal level)
The Differential nonlinearity for an output code i is the difference between the
measured step size of code i and the ideal LSB step size. DNL (i) is
expressed in LSBs. DNL is the maximum value of all DNL (i). DNL error
specification of less than 1 LSB guarantees that there are no missing output
codes and that the transfer function is monotonic
The Integral nonlinearity for an output code i is the difference between the
measured input voltage at which the transition occurs and the ideal value of
this transition. INL (i) is expressed in LSBs, and is the maximum value of all
INL (i)
Delay between the rising edge of the differential clock inputs (CLK,CLKB)
(zero crossing point), and the time at which (VIN,VINB) is sampled
ENOB
=
SINAD
--------------------------------------------------------------------------
–
1 76
⋅
6 02
⋅
+
20
log
------------ -
Fs 2 ⁄
A
Where A is the actual input
amplitude and F
range of the ADC under test
EV10AS008B
0811A–BDC–12/08
S
is the full-scale
±
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