FIN24AC Fairchild Semiconductor, FIN24AC Datasheet

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... TM © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 General Description The FIN24AC µSerDes™ low-power Serializer/ Deserializer (SerDes) that can help minimize the cost and power of transferring wide signal paths. Through the use of serialization, the number of signals transferred from one point to another can be significantly reduced. ...

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... Functional Block Diagram CKREF STROBE DP[21:22] DP[1:20] DP[23:24] CKP S1 S2 DIRI © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 Word PLL 0 Boundary Generator I cksint Serializer Control Serializer oe Deserializer Deserializer cksint Control WORD CK Generator Control Logic DIRO Freq. Direction Control Control oe Power Down Control Figure 1. Block Diagram ...

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... The DSO/DSI serial port terminals have been arranged such that when one device is rotated 180° to the other device, the serial connections properly align without the need for any traces or cable signals to cross. Other layout orientations may require that traces or cables cross. © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 Number of Terminals Description of Signals ...

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... Connection Diagrams DP[10] DP[11] DP[12] DP[13] DP[14] DP[15] DP[16] Figure 2. Terminal Assignments for MLP (Top View (Top View) © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 DP[ DDP CKP Pin Assignments DP[9] DP[7] DP[5] B DP[11] DP[10] DP[6] C CKP DP[12] DP[8] D DP[13] DP[14] V DDP E DP[15] DP[16] GND F DP[17] DP[18] DP[21] J DP[19] ...

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... Control Logic Circuitry The FIN24AC has the ability to be used as a 24-bit Seri- alizer or a 24-bit Deserializer. Pins S1 and S2 must be set to accommodate the clock reference input frequency range of the serializer. Table 1 shows the pin program- ming of these options based on the S1 and S2 control pins ...

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... No Data Figure 5. Serializer Timing Diagram (CKREF does not equal STROBE) © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 The Phase-Locked Loop (PLL) must receive a stable CKREF signal to achieve lock prior to any valid data being sent. The CKREF signal can be used as the data STROBE signal, provided that data can be ignored during the PLL lock phase ...

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... CKS0 No Data Figure 6. Serializer Timing Diagram Using Provided Bit Clock (No CKREF) © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 (Continued) A third method of serialization can be accomplished with a free running bit clock on the CKSI signal. This mode is enabled by grounding the CKREF signal and driving the DIRI signal HIGH. ...

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... Figure 8. Deserializer Timing Diagram (Serializer Source: CKREF does not equal STROBE) © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 When the DIRI signal is asserted LOW, the device is configured as a deserializer. Data is captured on the serial port and deserialized through use of the bit clock sent with the data ...

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... Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 resistor FIN24AC device is configured as an unidi- rectional serializer, unused data I/O can be treated as unused inputs. If the FIN24AC is hardwired as a deseri- alizer, unused data I/O can be treated as unused out- puts. From Deserializer ...

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... The output of the PLL is a bit clock that is used to serialize the data. The bit clock is also sent source syn- chronously with the serial data stream. © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 There are two ways to disable the PLL: by entering the Mode 0 state ( detecting a LOW on DS+ both the S1 and S2 signals ...

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... Generates an embedded word clock for each strobe signal. REFCK CNTL[0:1] Sending Unit DATA [0:19 Note: Data on serializer pins DP[21:22] is output on pins DP[23:24] of the deserializer. Figure 12. Unidirectional Serializer and Deserializer © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 Unidirectional Data Transfer BIT PLL Gen. – – Serializer CKSO CKSI Deserializer ...

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... Devices alternate frames of data controlled by a direction control and a direction sense. When DIRI on the right- hand FIN24AC is HIGH, data is sent from the camera to the camera interface at the base. When DIRI on the Flex Circuit Design Guidelines The serial I/O information is transmitted at a high serial rate. Care must be taken implementing this serial I/O flex cable. The following best practices should be used when developing the flex cabling or Flex PCB: ■ ...

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... Symbol Supply Voltage DDA DDS V Supply Voltage DDP T Operating Temperature A V Supply Noise Voltage DDA-PP © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 Parameter All Pins CKSO, CKSI, DSO to GND Parameter 13 Min. Max. Unit -0.5 +4.6 V -0.5 +4.6 V Continuous -65 +150 ° ...

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... Voltage is referenced to GROUND unless otherwise specified (except ΔV and the difference in device ground levels between the CTL driver and the CTL receiver. GO © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 Test Conditions V = 3.3 ± 0.3 DDP I = –2 2.5 ± 0.2 OH ...

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... CLKT Time t STROBE Pulse Width SPWH HIGH/LOW © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 Test Conditions All DP and Control Inputs CKREF DIR = 1 All DP and Control Inputs CKREF DIR = 0 All DP and Control Inputs ...

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... If the CKREF is not equal to STROBE for the serializer, the CKP signal does not maintain a 50% duty cycle. The low time of CKP remains 13 bit times. © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 Test Conditions CKREF x 26 ...

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... CKREF, STROBE, S1, S2, DIRI C Capacitance of Parallel Port Pins Capacitance of Differential I/O Signals IO-DIFF © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 Test Conditions DIRI LOW-to-HIGH or HIGH-to-LOW DIRI LOW-to-HIGH DIRI HIGH-to-LOW DIRI = 0, S1( and S2(1) = LOW-to-HIGH, Figure 29 (9) DIRI = 0, ...

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... Typical values are measured 2.5V TLH 80% V 20% DIFF V = (DS+) – (DS-) DIFF DS – DS- Figure 17. CTL Output Load and Transition Times © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 DS+ DUT DS- Figure 15. CTL Input Common Mode Test Circuit T 999h b b ...

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... Figure 21. Deserializer Data Valid Window Time and Clock Output Parameters t TCCD STROBE V DD/2 CKS0 DIFF CKS0+ Note: STROBE = CKREF Figure 23. Serializer Clock Propagation Delay © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 (Continued) Data t HTC CKREF t PDV 50% RCOL Note: CKREF signal is free running. CKSI- CKSI+ CKP Figure 24 ...

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... PLZ(HZ DS+,CKS0+ HIGH-Z DS-,CKS0- Note: CKREF must be active and PLL must be stable. Figure 29. Serializer Enable and Disable Time © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 (Continued) CKSO- t H_DS CKSO+ DSO+ DSO- Note: Data is typically edge aligned with the clock. ...

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... Sketch A (Side or Front Sectional View) Component Rotation Shipping Reel Dimension Dia A max Tape Dia A Dim B Width Max. Min. 8 330 1.5 12 330 1.5 16 330 1.5 © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0 Min. ±0.1 ±0.1 ±0.1 Typ ...

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... Sketch A (Side or Front Sectional View) Component Rotation Shipping Reel Dimension Dia A max Tape Dia A Dim B Width Max. Min. 8 330 1.5 12 330 1.5 16 330 1.5 © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 (Continued Min. ±0.1 ±0.1 ± ...

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... Dimensions are in millimeters unless otherwise noted. 2X 0.10 C TERMINAL A1 CORNER INDEX AREA (QA CONTROL VALUE) 1.00 MAX 0. SEATING PLANE Figure 31. Pb-Free, 42-Ball, Ultra Small Scale Ball Grid Array (USS-BGA), JEDEC MO-195, 3.5mm Wide © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 3.50 2X 0.10 C (0.6) 4.50 0.5 0.89±0.082 0.45±0.05 0.21±0.04 0.23±0.05 23 (0.35) (0.5) 2 ...

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... Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 32. Pb-Free, 40-Terminal, Molded Leadless Package (MLP), Quad, JEDEC MO-220, 6mm Square © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 (DATUM A) 24 www.fairchildsemi.com ...

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... Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 25 www.fairchildsemi.com ...