FIN3385 Fairchild Semiconductor, FIN3385 Datasheet - Page 16

• Manufacturer Part Number: FIN3385
• Description: Fin3385 * Fin3383 * Fin3384 * Fin3386 Low Voltage 28-bit Flat Panel Display Link Serializers/deserializers
• Manufacturer: Fairchild Semiconductor

www.fairchildsemi.com
AC Loading and Waveforms
Note: Test setup used considers no requirement for separation of RMS and deterministic jitter. Other hardware setup such as Wavecrest boxes can be used
if no M1 software is available, but the test methodology in Figure 20 should be followed.
Note: This jitter pattern is used to test the jitter response (Clock Out) of the device over the power supply range with worst jitter
input. The specific test methodology is as follows:
•
•
Note: t
Note: The minimum and maximum pulse position values are based on the bit position of each of the 7 bits within the LVDS data stream across PVT
(Process, Voltage Supply, and Temperature).
Switching input data TxIn0 to TxIn20 at 0.5 MHz, and the input clock is shifted to left
The
case of clock edge jump (3 ns) from graphical controllers. Cycle-to-cycle jitter at TxCLK out pin should be measured cross V
(V
CC
r
noise frequency
3 ns cycle-to-cycle input jitter is the static phase error between the two clock sources. Jumping between two clock sources to simulate the worst
RSKM
is the budget for the cable skew and source clock skew plus ISI (Inter-Symbol Interference).
2 MHz).
FIGURE 20. Timing Diagram of Transmitter Clock Input with Jitter
FIGURE 19. Transmitter Clock Out Jitter Measurement Setup
FIGURE 18. Receiver LVDS Input Skew Margin
(Continued)
16

3ns and to the right

3ns when data is HIGH.
CC
r
3ns (cycle-to-cycle) clock
range with 100mV noise