FIN3385 Fairchild Semiconductor, FIN3385 Datasheet
FIN3385
Available stocks
Related parts for FIN3385
FIN3385 Summary of contents
Page 1
... Low Voltage 28-Bit Flat Panel Display Link Serializers/Deserializers General Description The FIN3385 and FIN3383 transform 28 bit wide parallel LVTTL (Low Voltage TTL) data into 4 serial LVDS (Low Voltage Differential Signaling) data streams. A phase- locked transmit clock is transmitted in parallel with the data stream over a separate LVDS link ...
Page 2
... Block Diagrams Functional Diagram for FIN3385 and FIN3383 Receiver Functional Diagram for FIN3386 and FIN3384 www.fairchildsemi.com 2 ...
Page 3
... GND Connection Diagram FIN3383 and FIN3385 (28:4 Transmitter) Pin Assignment for TSSOP Description of Signals LVTTL Level Input LVTTL Level Clock Input The rising edge is for data strobe. Positive LVDS Differential Data Output Negative LVDS Differential Data Output 1 Positive LVDS Differential Clock Output ...
Page 4
RECEIVERS Pin Descriptions Number Pin Names I/O Type of Pins RxIn I 4/3 Negative LVDS Differential Data Input RxIn I 4/3 Positive LVDS Differential Data Input RxCLKIn I 1 Negative LVDS Differential Clock Input RxCLKIn I 1 ...
Page 5
Transmitter and Receiver Power-Up/Power-Down Operation Truth Table The outputs of the transmitter remain in the High-Impedance state until the power supply reaches 2V. The following table shows the operation of the transmitter during power-up and power-down and operation of the ...
Page 6
Absolute Maximum Ratings Power Supply Voltage ( TTL/CMOS Input/Output Voltage LVDS Input/Output Voltage LVDS Output Short Circuit Current (I ) OSD Storage Temperature Range (T ) STG Maximum Junction Temperature ( Lead Temperature ( ...
Page 7
... Transmitter Output Pulse Position of Bit 5 TPPB5 t Transmitter Output Pulse Position of Bit 6 TPPB6 t FIN3385 Transmitter Clock Out Jitter JCC (Cycle-to-Cycle) See Figure 20 t Transmitter Phase Lock Loop Set Time (Note 15) TPLLS Note 13: Outputs of all transmitters stay in 3-STATE until power reaches 2V. Both clock and data output begins to toggle 10ms after V Power-Down pin is above 1 ...
Page 8
Receiver DC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified. (Note 16) Symbol Parameter LVTTL/CMOS DC Characteristics V Input High Voltage IH V Input Low Voltage IL V Output High Voltage OH V Output Low Voltage ...
Page 9
Receiver AC Electrical Characteristics (66MHz) Symbol Parameter t Receiver Clock Output (RxCLKOut) Period RCOP t RxCLKOut LOW Time RCOL t RxCLKOut HIGH Time RCOH t RxOut Valid Prior to RxCLKOut RSRC t RxOut Valid After RxCLKOut RHRC t RxCLKOut LOW ...
Page 10
FIGURE 1. Differential LVDS Output DC Test Circuit Note A: For all input pulses Note B: C includes all probe and jig capacitance. L FIGURE 2. Differential Receiver Voltage Definitions and Propagation Delay and Transition Time Test Circuit ...
Page 11
AC Loading and Waveforms Note: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVTTL/CMOS I/O. Depending on the valid strobe edge of transmitter, the TxCLKIn can be either rising or falling edge data ...
Page 12
AC Loading and Waveforms FIGURE 7. Transmitter Outputs Channel-to-Channel Skew Note: For the receiver with falling-edge strobe, the definition of setup/hold time will be slightly different from the one with rising-edge strobe. The clock refer- ence point is the time ...
Page 13
AC Loading and Waveforms FIGURE 11. Receiver Phase Lock Loop Set Time FIGURE 12. Transmitter Power-Down Delay FIGURE 13. Receiver Power-Down Delay (Continued) 13 www.fairchildsemi.com ...
Page 14
AC Loading and Waveforms Note: The information in this diagram shows the relationship between clock out and the first data bit. A 2-bit cycle delay is guaranteed when the MSB is out- put from the transmitter. FIGURE 14. 28 Parallel ...
Page 15
AC Loading and Waveforms FIGURE 16. Transmitter Output Pulse Bit Position FIGURE 17. Receiver Input Bit Position (Continued) 15 www.fairchildsemi.com ...
Page 16
AC Loading and Waveforms Note the budget for the cable skew and source clock skew plus ISI (Inter-Symbol Interference). RSKM Note: The minimum and maximum pulse position values are based on the bit position of each of the ...
Page 17
AC Loading and Waveforms Note: The 16-grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical strips across the display. FIGURE 21. “16 Grayscale” ...
Page 18
Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...