ADT7473 Analog Devices, Inc., ADT7473 Datasheet - Page 22

• Manufacturer Part Number: ADT7473
• Description: Dbcool Remote Thermal Monitor And Fan Controller
• Manufacturer: Analog Devices, Inc.

ADT7473
Handling SMBALERT Interrupts
To prevent the system from being tied up servicing interrupts, it
is recommended to handle the SMBALERT interrupt as follows:
1.
2.
3.
4.
5.
6.
Periodically poll the status registers. If the interrupt status bit
has cleared, reset the corresponding interrupt mask bit to 0.
This causes the SMBALERT output and status bits to behave as
shown in Figure 27.
Masking Interrupt Sources
Register 0x74, Interrupt Mask Register 1
Register 0 x75, Interrupt Mask Register 2
These registers allow individual interrupt sources to be maske
out to prevent SMBALERT interrupts. Masking an interrupt
source prevents only the SMBALERT output from being
asserted; the appropriate status bit is set normally.
Interrupt Mask Register 1 (0x74)
Bit 7 (OOL) = 0, when one or more alerts are generated in
Interrup
Interrupt Mask Register 2 (0x75) =1
ass rted.
OO =1, when one or more alerts are generated in Interrupt
Sta s Register 2, assuming all the mask bits in the Interrupt
Mas
Bit 6 (R2T) = 1, masks SMBALERT for Remote 2 temperature
HIGH LIMIT
TEMPERATURE
STATUS BIT
SMBALERT
STICKY
Figure 27. How Masking the Interrupt Source Affects SMBALERT Output
e
tu
L
k Register 2 (0x75) =1; SMBALERT is not asserted.
Detect the SMBALERT assertion.
Enter the interrupt handler.
Read the status registers to identify the interrupt source.
Mask the interrupt source by setting the appropriate mask
bit in the interrupt mask registers (Register 0x74 and
Register 0x75).
Take the appropriate action for a given interrupt source.
Exit the interrupt handler.
t Status Reg
ister 2, assumin
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
INTERRUPT
MASK BIT SET
g all the mask bits in the
; SMBALERT is still
(TEMP BELOW LIMIT)
CLEARED ON REA
(SMBALERT RE-ARMED)
INTERRUPT MASK BI
CLEARED
D
T
Rev. A | Page 22 of 76
d
Bit 5 (LT) = 1, masks SMBALERT for local temperature.
Bit 4 (R1T) = 1, masks SMBALERT for Remote 1 temperature.
Bit 2 (V
Bit 1
Interrupt Mask Register 2 (Reg. 0x75)
Bit 7 (D2) = 1, mas s SMBALERT for Diode 2 errors.
Bit 6 (D1) = 1, masks SMBALERT for Diode 1 errors.
Bit 5 (FAN4) = 1, masks SMBAL RT
If the TACH4 pin is being used as the THERM input, this bit
masks SMBALERT for a THERM event.
Bit 4 (FAN3) = 1, masks SMBALERT for Fan 3.
Bit 3 (FAN2) = 1, masks SMBALERT for Fan 2.
Bit 2 (FAN1) = 1, masks SMBALERT for Fan 1.
Bit 1 (OVT) = 1, masks SMBALERT for overtemperature
(exceeding THERM limits).
Enabling the SMBALERT Interrupt Output
The SMBALERT interrupt function is disabled by default. Pin 5
or Pin 9 can be reconfigured as an SMBALERT output to signal
out-of-limit conditions.
Table 13. Configuring Pin 5 as SMBALERT Output
Register
Configuration Register 3 (0x78)
Assigning THERM Functionality to a Pin
Pin 9 on the ADT7473 has four possible functions:
SMBALERT , THERM , GPIO, and TACH4. The user chooses
the required functionality by setting Bit 0 and Bit 1 of
Configuration Register 4 (0x7D).
Bit1
0
0
1
1
Once Pin 9 is configured as THERM , it must be enabled by
setting Bit 1 of Configuration Register 3 (0x78).
THERM as an Input
When THERM is configured as an input, the ADT7473 can
time assertions on the THERM pin. This can be useful for
connecting to the PROCHOT output of a CPU to gauge system
performance. See the THERM Timer section for more
information.
(V
CC
CCP
) = 1, masks SMBALERT for V
) = 1, masks SMBA
Bit 0
1
0
1
0
k
LERT
E
Function
TACH4
THERM
SMBus ALERT
GPIO
for V
for Fan 4 failure.
CC
CCP
channel.
channel.
Bit Setting
[0] ALERT = 1