ADT7473 Analog Devices, Inc., ADT7473 Datasheet - Page 13

• Manufacturer Part Number: ADT7473
• Description: Dbcool Remote Thermal Monitor And Fan Controller
• Manufacturer: Analog Devices, Inc.

READ OPERATIONS
The ADT7473 uses the following SMBus read protocols.
Receive Byte
This operation is useful when repeatedly r
register. The reg
In this operation, the master device receives a
slave device, as follows:
1.
2.
3.
4.
5.
6.
In the ADT7473, the receive byte protocol is us
single byte of data from
been set by a send byte or write byte operation. This opera
is illustrated in Figure 19.
Alert Response Address
Alert response address (ARA) is a feature of SMBus devices that
allows an interrupting device to identify itself to the host when
multiple devices exist on the same bus.
The SMBALERT output can be used as either an interrupt
output or an SMBALERT . One or more outputs can be
connected to a common SMBALERT line connected to the
master. If a device’s SMBALERT line goes low, the following
events occur:
•
•
•
•
SMBALERT is pulled low.
The master initiates a read operation and sends the alert
response address (ARA = 0001 100). This is a general call
address that must not be used as a specific device address.
The device whose SMBALERT output is low responds to
the alert response address, and the master reads its device
address. The address of the device is now known and can
be interrogated in the usual way.
If more than one device’s SMBALERT output is low, the
one with the lowest device address has priority in accor-
dance with normal SMBus arbitration.
The master device asserts a start condition on SDA.
The master sends the 7-b
read bit (high).
The addressed slave device asserts ACK on SDA.
The master receives a data byte.
The master asserts NO ACK on SDA.
The master asserts a s
transaction ends.
Figure 19. Single-Byte Read from a Register
iste
S
1
ADDRESS
r address must have been pre
SLAVE
2
a register whose address has previously
top condition on SDA, and the
R
it slave address followed by the
A
3
DATA
4
5 6
A P
eading a single
single byte from a
ed to read a
viously set up.
tion
Rev. A | Page 13 of 76
Once the ADT7473 has responded to t
the master must read the status registers, and the SMBALERT is
cleared only if the error condition is gone.
SMBus TIMEOUT
The ADT7473 includes an SMBus timeout feature. If there is n
SMBus activity for 35 ms, the ADT7473 ass
locked and releases the bus. This prev
locking or holding the SMBus expecting data. Some SMBus
controllers cannot work with the SMBus timeout feature, so it
can be disabled.
Configuration Register 1 (0x40)
Bit 6 TODIS = 0; SMBus timeout enabled (default)
Bit 6 TODIS = 1; SM
VOLTAGE MEASU
The
and c
meas
out t
mon
ANALOG-TO-DIGITAL CONVE
All analog inputs are mu
approximation, analog-to-digital co
tion of 10 bits. The basic input rang
input has built-in attenuators to allow m
without any external components. To allow for th
the supply voltage, the ADC produces an output o
(768 decimal or 300 hex) for the nominal input voltage and thus
has adequate headroom to deal with overvoltages.
INPUT CIRCUITRY
The internal structure for the V
Figure 20. The input circuit consists of an input protection
diode, an attenuator, plus a capacitor to form a first order
low-pass filter that gives the input immunity to high frequency
noise.
VOLTAGE MEASUREMENT REGISTERS
Register 0x21 V
Register 0x22 V
ADT7473 has one external vol
hrough the V
itor a chipset supply voltage in
ure V
an also measure its own supp
CCP
. The V
V
CCP
CC
CCP
Figure 20. Structure of Analog Inputs
CC
Reading = 0x00 default
Reading = 0x00 default
pin (Pin 3). Th
Bus timeout disabled
CC
REMENT I
supply volt
17.5kΩ
ltiplexed into the on-chip, successive
52.5kΩ
CCP
age measurement is carrie
ly vo
NPUT
tage m
analog input is shown in
e V
computer systems.
e is 0 V to 2.25 V, but the
nverter. This has a resolu-
RTER
ents the device from
he alert response address,
CCP
ltage, V
easurement of V
easurement channel
input can be
35pF
umes the bus is
CC
. Pin 14 can
e tolerance of
f ¾ full scale
ADT7473
used to
CCP
d
o